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$$\hbox {TM}^{2}$$ TM 2 C: a software transactional memory for many-cores

$$\hbox {TM}^{2}$$ TM 2 C: a software transactional memory for many-cores Transactional memory is an appealing paradigm for concurrent systems. Many software implementations of the paradigm were proposed in the past two decades for both shared memory multi-core systems and clusters of distributed machines. Chip manufacturers have however started producing many-core architectures, with low network-on-chip communication latencies and limited support for cache coherence, rendering existing transactional-memory implementations inapplicable. This paper presents $$\hbox {TM}^{2}\hbox {C}$$ TM 2 C , the first software transactional memory protocol for many-core systems, hence featuring transactions that are both distributed and leverage shared memory. $$\hbox {TM}^{2}\hbox {C}$$ TM 2 C exploits fast messages over network-on-chip to make accesses to shared data coherent. In particular, it allows visible read accesses to detect conflicts eagerly and incorporates the first distributed contention manager that guarantees the commit of all transactions. We evaluate $$\hbox {TM}^{2}\hbox {C}$$ TM 2 C on Intel, AMD and Tilera architectures, ranging from common multi-cores to experimental many-cores. We build upon new message-passing protocols, based on both software and hardware, which are interesting in their own right. Our results on various benchmarks, including realistic banking and MapReduce applications, show that $$\hbox {TM}^{2}\hbox {C}$$ TM 2 C scales well regardless of the underlying platform. http://www.deepdyve.com/assets/images/DeepDyve-Logo-lg.png Distributed Computing Springer Journals

$$\hbox {TM}^{2}$$ TM 2 C: a software transactional memory for many-cores

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References (79)

Publisher
Springer Journals
Copyright
Copyright © 2017 by Springer-Verlag GmbH Germany
Subject
Computer Science; Computer Communication Networks; Computer Hardware; Computer Systems Organization and Communication Networks; Software Engineering/Programming and Operating Systems; Theory of Computation
ISSN
0178-2770
eISSN
1432-0452
DOI
10.1007/s00446-017-0310-6
Publisher site
See Article on Publisher Site

Abstract

Transactional memory is an appealing paradigm for concurrent systems. Many software implementations of the paradigm were proposed in the past two decades for both shared memory multi-core systems and clusters of distributed machines. Chip manufacturers have however started producing many-core architectures, with low network-on-chip communication latencies and limited support for cache coherence, rendering existing transactional-memory implementations inapplicable. This paper presents $$\hbox {TM}^{2}\hbox {C}$$ TM 2 C , the first software transactional memory protocol for many-core systems, hence featuring transactions that are both distributed and leverage shared memory. $$\hbox {TM}^{2}\hbox {C}$$ TM 2 C exploits fast messages over network-on-chip to make accesses to shared data coherent. In particular, it allows visible read accesses to detect conflicts eagerly and incorporates the first distributed contention manager that guarantees the commit of all transactions. We evaluate $$\hbox {TM}^{2}\hbox {C}$$ TM 2 C on Intel, AMD and Tilera architectures, ranging from common multi-cores to experimental many-cores. We build upon new message-passing protocols, based on both software and hardware, which are interesting in their own right. Our results on various benchmarks, including realistic banking and MapReduce applications, show that $$\hbox {TM}^{2}\hbox {C}$$ TM 2 C scales well regardless of the underlying platform.

Journal

Distributed Computing – Springer Journals

Published: Aug 28, 2017

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