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Design and performance analysis of buffer inserted on-chip global nano interconnects in VDSM technologies

Design and performance analysis of buffer inserted on-chip global nano interconnects in VDSM... This work presents a novel buffer inclusion method has been proposed through Schmitt trigger in advanced CNT interconnects to increase the performance of VLSI circuits. On continues scaling of technology, signal integrity problems occurs and they affect transition time and fan-out. In order to troubleshoot this, active buffers are introduced at the intermediate stages of VLSI interconnects. In this work, we have analyzed a Schmitt trigger as a buffer in interconnects instead of using complementary metal oxide semiconductor (CMOS) buffers, with different interconnect materials such as copper, single-walled carbon nanotube (SWCNT) and multi-walled carbon nanotube (MWCNT). Further, an advanced Schmitt trigger buffer using carbon nanotube field effect transistor (CNFETs) is also analyzed and compared its performance with CMOS technology, found that delay is decreased by 30% and power is saved by 55%. Later, noise analysis is done by applying various noisy signal levels at inputs of the buffers. It is observed that Schmitt trigger buffer has been reduced noise peaks compared to CMOS buffers. Further, it is observed from SPICE simulations that CNFET Schmitt triggers shows less noise and less far-end delay while compare with MOS based Schmitt trigger buffers in interconnects. http://www.deepdyve.com/assets/images/DeepDyve-Logo-lg.png Nanotechnology for Environmental Engineering Springer Journals

Design and performance analysis of buffer inserted on-chip global nano interconnects in VDSM technologies

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References (32)

Publisher
Springer Journals
Copyright
Copyright © The Author(s), under exclusive licence to Springer Nature Switzerland AG 2022
ISSN
2365-6379
eISSN
2365-6387
DOI
10.1007/s41204-022-00249-x
Publisher site
See Article on Publisher Site

Abstract

This work presents a novel buffer inclusion method has been proposed through Schmitt trigger in advanced CNT interconnects to increase the performance of VLSI circuits. On continues scaling of technology, signal integrity problems occurs and they affect transition time and fan-out. In order to troubleshoot this, active buffers are introduced at the intermediate stages of VLSI interconnects. In this work, we have analyzed a Schmitt trigger as a buffer in interconnects instead of using complementary metal oxide semiconductor (CMOS) buffers, with different interconnect materials such as copper, single-walled carbon nanotube (SWCNT) and multi-walled carbon nanotube (MWCNT). Further, an advanced Schmitt trigger buffer using carbon nanotube field effect transistor (CNFETs) is also analyzed and compared its performance with CMOS technology, found that delay is decreased by 30% and power is saved by 55%. Later, noise analysis is done by applying various noisy signal levels at inputs of the buffers. It is observed that Schmitt trigger buffer has been reduced noise peaks compared to CMOS buffers. Further, it is observed from SPICE simulations that CNFET Schmitt triggers shows less noise and less far-end delay while compare with MOS based Schmitt trigger buffers in interconnects.

Journal

Nanotechnology for Environmental Engineering – Springer Journals

Published: Sep 1, 2022

Keywords: Carbon nanotube FETs (CNFETs); CMOS; Schmitt trigger; Buffer; Interconnects

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