Enhanced Fault Current-Limiting Circuit Design for a DC Fault in a Modular Multilevel Converter-Based High-Voltage Direct Current System

Kaipei Liu; Qing Huai; Liang Qin; Shu Zhu; Xiaobing Liao; Yuye Li; Hua Ding

doi:10.3390/app9081661

Enhanced Fault Current-Limiting Circuit Design for a DC Fault in a Modular Multilevel Converter-Based High-Voltage Direct Current System

Liu, Kaipei;Huai, Qing;Qin, Liang;Zhu, Shu;Liao, Xiaobing;Li, Yuye;Ding, Hua 2019-04-22 00:00:00 applied sciences Article Enhanced Fault Current-Limiting Circuit Design for a DC Fault in a Modular Multilevel Converter-Based High-Voltage Direct Current System 1 1 , 1 , 1 1 1 Kaipei Liu , Qing Huai * , Liang Qin * , Shu Zhu , Xiaobing Liao , Yuye Li and Hua Ding School of Electrical Engineering and Automation, Wuhan University, Wuhan 430072, China; kpliu@whu.edu.cn (K.L.); whuzhushu@163.com (S.Z.); xbliao@whu.edu.cn (X.L.); liyuye@whu.edu.cn (Y.L.) State Grid Energy Conservation Service Co., Ltd., Beijing 100052, China; huaworking@163.com * Correspondence: qinghuai315@whu.edu.cn (Q.H.); qinliang@whu.edu.cn (L.Q.); Tel.: +86-1347-683-0019 (Q.H.); +86-1898-617-2977 (L.Q.) Received: 20 March 2019; Accepted: 18 April 2019; Published: 22 April 2019 Abstract: The main weakness of the half-bridge modular multilevel converter-based high-voltage direct current (MMC-HVDC) system lies in its immature solution to extremely high current under direct current (DC) line fault. The development of the direct current circuit breaker (DCCB) remains constrained in terms of interruption capacity and operation speed. Therefore, it is essential to limit fault current in the MMC-HVDC system. An enhanced fault current-limiting circuit (EFCLC) is proposed on the basis of fault current study to restrict fault current under DC pole-to-pole fault. Speciﬁcally, the EFCLC consists of fault current-limiting inductance L and energy dissipation FCL resistance R in parallel with surge arrestor. L reduces the fault current rising speed, together FCL FCL with arm inductance and smoothing reactor. However, in contrast to arm inductance and smoothing reactor, L will be bypassed via parallel-connected thyristors after blocking converter to prevent FCL the eect on fault interruption speed. R shares the stress on energy absorption device (metal FCL oxide arrester) to facilitate fault interruption. The DCCB requirement in interruption capacity and breaking speed can be satisﬁed eortlessly through the EFCLC. The working principle and parameter determination of the EFCLC are presented in detail, and its eectiveness is veriﬁed by simulation in RT-LAB and MATLAB software platforms. Keywords: fault current-limiting circuit; DC circuit breaker; MMC-HVDC; fault protection 1. Introduction Fault vulnerability and protection immaturity constrain the development of the voltage source converter-based high-voltage direct current (VSC-HVDC) system, especially in terms of DC side fault at high power levels. Thus, reliability has become an important challenge in multilevel converter-based (MMC)-HVDC with long-distance transmission lines [1,2]. The lack of a perfect fault isolation scheme and mature DC switchgear products are the primary issues [3]. However, the VSC-HVDC system has attracted worldwide attention and research interests due to its advantages with respect to control ﬂexibility and interconnection feasibility. A related analysis of DC faults has been performed to enhance its fault ride through (FRT) ability under DC fault in the VSC-HVDC system [4,5]. An overview of HVDC system protection mentions that the major limitation in development of VSC-HVDC is the inability to limit fault current, given the limitation of the DC circuit breaker (DCCB) in interruption capability and operation speed [6]. Moreover, limiting fault current can protect the semiconductor device from excessive electrical pressure, particularly insulated gate bipolar thyristor (IGBT) and Appl. Sci. 2019, 9, 1661; doi:10.3390/app9081661 www.mdpi.com/journal/applsci Appl. Sci. 2019, 9, 1661 2 of 26 freewheeling diode in a converter sub-module (SM). Furthermore, restriction of fault current can provide additional time for fault detection and operation delay. Therefore, limiting fault current development and propagation in the VSC-HVDC and multi-terminal HVDC (MTDC) systems is essential. State-of-the-art fault current-limiting (FCL) techniques can be classiﬁed into improved SM topologies [7–12], auxiliary FCL circuits (FCLC) [13–20], and fault current limiters [21–25]. The SM topology has been modiﬁed to reinforce its fault handling ability, because the classical half-bridge SM (HBSM) is likely to be destroyed under overcurrent if no proper protection scheme is applied, even if insulated gate bipolar translators (IGBTs)are blocked in a timely fashion [26]. Thus, several innovative improvements, including full-bridge SM (FBSM) [7,8], clamp double SM (CDSM) [9], and hybrid SM, which combines FBSM and HBSM, have been conceived in the SM topology design [10]. Although the FBSM solution can ride through faults without blocking the converter, given its ability to output bipolar voltage, regardless of arm current direction [9], the doubled number and on-state loss of semiconductors are their main drawbacks. A CDSM solution only has 50% higher semiconduction than the HBSM to extinguish the DC arc by blocking IGBTs under nonpermanent fault [10]. However, the MMC converter has generally been regarded as the most appropriate static synchronous compensator to support alternating current (AC) grids in DC pole-to-pole fault scenarios [11]. Thus, enhancing the FRT capability without blocking the converter is crucial. A hybrid MMC topology requires each arm to have the same amount of FBSM and HBSM by considering their nature [10,12]. Thus, the cost of semiconductor devices and conduction losses have been reduced in comparison with those in the FBSM. However, further research on control strategies in terms of dynamic characteristics and SM voltage balancing is required [2]. Overall, control complexity and high cost are the weaknesses of SM topology-based solutions. Another FCL technology relies on an auxiliary circuit, which consistently includes energy dissipation resistance and an FCL reactor. For example, a hybrid current-limiting circuit (Figure 1a) has been designed to restrain the DC line fault current in the MTDC system [13], which is settled at the end of the DC line between the DCCB and DC converter ports. The energy dissipation resistance R is equipped to share the stress on energy absorption element in the DCCB, and the fault current interruption speed is accelerated. However, the tradeo between FCL performance and the extra cost of the resistor must be considered. In addition, a bridge-type FCLC is composed of a DC voltage source, a DC reactor, and four groups of diodes (Figure 1b) [14]. Reference [14] shows that the DC biased current given by the DC power supply is considered to be the threshold value of the DC fault current in order to automatically activate the FCLC itself. The main advantage is that the DC reactor can be bypassed in its normal state and after turning o the main breaker of the DCCB. In addition, the idea of the FCLC is also reﬂected in the form of an SM [15], which is inserted into each arm in series. However, the FCL-SM can only limit a unidirectional fault current, and the surge voltage across FCL-SM must be given further attention. Moreover, an enhanced reverse blocking SM (ERBSM) topology has been proposed to extinguish a fault current arc by inverse voltage [16]. Control complexity is reduced because the ERBSM adopts the same modulation strategy. In Reference [17], thyristors have better performance than diode in withstanding overcurrent (Figure 1e), and the overcurrent pressure on freewheeling diode has been relieved via the shunting eect of a single-thyristor switch scheme (STSS) [17–19]. Although the STSS can protect semiconductor devices, the AC grid current fed into the DC side cannot be prevented. Thus, the double-thyristor switch scheme (DTSS) has been introduced to protect the DC overhead line (Figure 1f), which can eliminate the freewheeling eect of diodes, and the DC line fault current can freely decay to zero [20]. Then, the DC fault is transformed into an AC short circuit fault that can be cleared by switching o the thyristor. However, the high dv/dt across thyritors and the sharing current eect of bypassed diodes are ignored in the DTSS solution. To solve this problem, double-thyristor switches are combined and connected at the AC port of the converter instead of across the diode in the SM to isolate the AC side from the DC side when a fault occurs. Moreover, the feasibility of such a scheme has been veriﬁed via a case study that considers STSS and DTSS in a classical VSC-HVDC system, as well as MMC-HVDC. Appl. Sci. 2019, 9, 1661 3 of 26 The superconducting fault limiter (SFCL) has attracted considerable attention because its nonlinear impedance characteristics can be used to limit the increase in fault current rate to provide a necessary time for relay protection. The SFCL can mainly be divided into resistive-SFCL (R-SFCL) and inductive-SFCL (I-SFCL) [21]. The study concludes that R-SFCL can constrain the amplitude of fault current, but reduces the increase in fault current rate dierently, and I-SFCL can delay the increase in fault rate signiﬁcantly [22]. Related research has been performed on the basis of the unique characteristics in SFCL. For example, R-SFCL has been thoroughly investigated on the basis of the current-limiting capability comparison and parameter inﬂuence, thus indicating that the use of R-SFCL is suggested for real applications, provided that it is suciently sensitive to develop an adequate quenching resistance [23]. Hybrid DCCB has been equipped with SFCL in the main line to limit the fault current until a fault is completely interrupted [24,25]. In addition, the superconducting magnetic energy storage technique has been adopted to limit fault current, which is achieved via a power transform between the power system and superconducting coil [26]. A rapid limitation can be realized when controlled FCL (molded as pancakes) is isolated to maintain its dynamic stability. In contrast to the AC line fault current, the fault current under DC short circuit fault in the MMC-HVDC system does not have a natural zero crossing. Thus, applying DCCB has been limited given its high cost and technical immaturity [27]. Mechanical breakers can limit fault current in a few tens of milliseconds but cannot satisfy the demand in the VSC-HVDC system protection [28]. Although semiconductor circuit breakers have a large on-state loss, the operation speed requirement is satisﬁed. The hybrid HVDC breaker has been proposed and investigated in References [29–31] to eliminate on-state power loss and limit fault current within several milliseconds. Parametric analysis of hybrid DCCB has also been conducted thoroughly considering the inﬂuence of the main parameters on the system and the breaker design [32]. Moreover, an interlink DCCB has been proposed to maintain the fault current interruption ability with a few components to reduce the overall cost of the DCCB in the DC grid [33]. In Reference [24], varying the DC current is considered an underdamping decay process, given the small resistance in the fault circuit. Thus, the fault current-limiting inductance L cannot change FCL the damping characteristics which refer to criterion R < 2 L/C. That is, L can only limit DC fault FCL current, but not relieve the overcurrent eect in the converter and AC sides [24]. The SFCL has not been applied extensively in real projects because of its high cost and lack of maturity, particularly with respect to SFCL recovery after being activated. The main advantage of the SFCL is that it does not inﬂuence the dynamic response under normal state. The direct installation of the DC reactor aects the system’s normal operation and DCCB isolation speed [34]. Therefore, the present study proposes an enhanced fault current-limiting circuit (EFCLC) that primarily consists of energy dissipation resistance, limiting reactor, surge arrester, and semiconductor switches on the basis of existing works. The EFCLC aims to limit fault current through converter arms and DC line before the DCCB operates, thereby decreasing the peak current for fault interruption and reducing overcurrent eect on converter arms. Moreover, the required DCCB capability could be reduced, given limited fault current with EFCLC and more time is saved for fault detection, since fault current rising speed is more or less restricted. The remainder of this paper is organized as follows. Section 2 thoroughly analyzes DC fault current on the basis of theoretical calculation and simulation veriﬁcation. Section 3 presents the topology and working principle of EFCLC. Section 4 performs the parametric design study of EFCLC. Section 5 further investigates the proposed scheme with EFCLC in terms of FCL ability and cost. Finally, Section 6 summarizes the conclusion and future scope. 2. DC Fault Current Analysis 2.1. Test System Introduction The scheme of the MMC-HVDC system can be categorized into monopolar and bipolar symmetrical wiring systems (Figure 1). The monopolar symmetrical HVDC system is also known as the pseudo Appl. Sci. 2019, 9, 1661 4 of 26 Appl. Sci. 2019, 9, x 4 of 26 bipolar HVDC system, which typically adopts a cable as a DC line. However, a real bipolar HVDC system is commonly applied in the HVDC transmission system with a high-capacity and overhead DC bipolar HVDC system is commonly applied in the HVDC transmission system with a high-capacity line. The main dierence between the two schemes lies in operation mode. Bipolar systems can work and overhead DC line. The main difference between the two schemes lies in operation mode. Bipolar under both monopolar mode and bipolar mode. Namely, the power transmission of the positive pole systems can work under both monopolar mode and bipolar mode. Namely, the power transmission overhead line and negative pole overhead line is independent. Therefore, bipolar systems can work of the positive pole overhead line and negative pole overhead line is independent. Therefore, bipolar during fault by transferring power through healthy line (monopolar mode). In contrast, monopolar systems can work during fault by transferring power through healthy line (monopolar mode). In systems cannot maintain power transmission under fault, since they only operate under monopolar contrast, monopolar systems cannot maintain power transmission under fault, since they only mode. Hence, the bipolar system demonstrates advantages in terms of power supply reliability and operate under monopolar mode. Hence, the bipolar system demonstrates advantages in terms of FRT capability. power supply reliability and FRT capability. Positive pole cable MMC Negative pole cable MMC (a) Positive pole overhead line MMC MMC Metallic return MMC MMC Negative pole overhead line (b) Figure 1. Diagram of the modular multilevel converter-based high-voltage direct current system in Figure 1. Diagram of the modular multilevel converter-based high-voltage direct current system in (a) (a) monopolar symmetrical wiring and (b) bipolar symmetrical wiring. monopolar symmetrical wiring and (b) bipolar symmetrical wiring. The MMC-HVDC system mainly consists of modular multilevel converter stations and DC line The MMC-HVDC system mainly consists of modular multilevel converter stations and DC line part parts. s. The t The topology opology st str ructur ucture of e of MMC, MMC, which which inc includes ludesthr thee ree convert converter er unit units,sis , is displayed displayed in in Figur Figu ere 2. Each unit involves upper and lower bridge arms that are connected with the bridge arm reactor L . 2. Each unit involves upper and lower bridge arms that are connected with the bridge arm reactor 𝐿 . The SMs ar The SMs aree connected connected in in series serie in s every in ever bridge y bridge arm, arm which , wh consists ich conof sists o twofswitches, two switches, name namely, T and ly, T 𝑇 1 2 (IGBT); anti-parallel connected diodes, namely, D and D ; and energy storage capacitor C . The DC and 𝑇 (IGBT); anti-parallel connected diodes, namely, 𝐷 and 𝐷 ; and energy storage capacitor 𝐶 . 1 2 0 The DC volt voltage is maintained age is maby inta switch ined by sw ing T it and ching T 𝑇on and and o 𝑇 in onevery and o SM ff in tripped every S by Ma tcontr ripped by ol signal. a cont If the rol 1 2 amount of SMs in each converter unit is 2N, then it has N switched-on and N switched-o SMs during signal. If the amount of SMs in each converter unit is 2N, then it has N switched-on and N switched- off SMs during normal operation. normal The DC operat sideion. voltage The U DC side vo is equalltto agthe e 𝑈 sum is e of q the uaswitched-on l to the sum of SMth voltage e switched- U . The on DC 0 main modulation modes are divided into pulse width modulation and nearest level modulation. The SM voltage 𝑈 . The main modulation modes are divided into pulse width modulation and nearest level converter modu stations lation. The conv are blocked erte by r st turning ations are o block IGBTs ed in by t all u SMs rning given off IG the BTs in local al over l SM curr s given ent pr tote he ction local when a current reaches a threshold value (normally twice the value of the nominal current). overcurrent protection when a current reaches a threshold value (normally twice the value of the nominal current). Appl. Sci. 2019, 9, 1661 5 of 26 Appl. Sci. 2019, 9, x 5 of 26 Figure 2. Topology structure of the MMC. Figure 2. Topology structure of the MMC. 2.2. DC Fault Analysis of the Test System 2.2. DC Fault Analysis of the Test System In the monopolar MMC-HVDC system, the DC line is typically composed of cables because the In the monopolar MMC-HVDC system, the DC line is typically composed of cables because the fault possibility is considered much lower in cables than in overhead lines [35]. However, an overhead fault possibility is considered much lower in cables than in overhead lines [35]. However, an line is typically adopted in the bipolar system, especially in long-distance power transmission with a overhead line is typically adopted in the bipolar system, especially in long-distance power high capacity. Given that an overhead line is likely to be aected by a short circuit, grounded fault, and transmission with a high capacity. Given that an overhead line is likely to be affected by a short nonpermanent fault, analyzing the fault characteristics for protection relaying is necessary. The DC circuit, grounded fault, and nonpermanent fault, analyzing the fault characteristics for protection line faults are mainly classiﬁed into a single pole-to-ground fault, pole-to-pole short-circuit fault (PPF), relaying is necessary. The DC line faults are mainly classified into a single pole-to-ground fault, pole- and line disconnection. The PPF is regarded as a serious fault considering an extremely high fault to-pole short-circuit fault (PPF), and line disconnection. The PPF is regarded as a serious fault current within a few milliseconds after fault occurrence. In Figure 2, the MMC-HVDC scheme indicates considering an extremely high fault current within a few milliseconds after fault occurrence. In Figure that the single pole-to-ground fault in the bipolar system can be equivalent to the PPF given bipolar 2, the MMC-HVDC scheme indicates that the single pole-to-ground fault in the bipolar system can system’s metallic return is connected to ground. Therefore, the PPF is selected to be investigated in be equivalent to the PPF given bipolar system’s metallic return is connected to ground. Therefore, the this study, especially in terms of fault current. Fault current propagation can be segmented into SM PPF is selected to be investigated in this study, especially in terms of fault current. Fault current capacitor discharging before blocking IGBT, decayed freewheeling current, and AC gird in-feed current propagation can be segmented into SM capacitor discharging before blocking IGBT, decayed after blocking IGBT. Before blocking IGBT, the discharging capacitor in inserted SMs leads to surge freewheeling current, and AC gird in-feed current after blocking IGBT. Before blocking IGBT, the current, which provides a high electrical pressure on semiconductor devices. Thus, from a protection discharging capacitor in inserted SMs leads to surge current, which provides a high electrical perspective, IGBT is blocked with a control signal when the arm current reaches the threshold value. pressure on semiconductor devices. Thus, from a protection perspective, IGBT is blocked with a control signal when the arm current reaches the threshold value. 2.2.1. Submodule Capacitor Discharging Period At the beginning of the PPF, the capacitor in every inserted SM discharges and bridge arm current 2.2.1. Submodule Capacitor Discharging Period surges. Figure 3 depicts the fault current circuit, in which the capacitor discharging current ﬂows At the beginning of the PPF, the capacitor in every inserted SM discharges and bridge arm through the IGBT of the inserted SMs and the anti-parallel diode of the removed SMs in each converter current surges. Figure 3 depicts the fault current circuit, in which the capacitor discharging current unit. The fault occurs at point A and point B, which are connected with dashed line in Figure 3. flows through the IGBT of the inserted SMs and the anti-parallel diode of the removed SMs in each Considering that converter includes six arms with same topology, hence, only the upper arm of phase converter unit. The fault occurs at point A and point B, which are connected with dashed line in A is shown with insert SMs and removed SMs due to the space of ﬁgure and simplicity. All the IGBT Figure 3. Considering that converter includes six arms with same topology, hence, only the upper can be turned o as the bridge arm current reaches the threshold value to protect the IGBT from arm of phase A is shown with insert SMs and removed SMs due to the space of figure and simplicity. overcurrent damage. The voltage cross converter unit v decreases with SM capacitor discharging conv All the IGBT can be turned off as the bridge arm current reaches the threshold value to protect the until the IGBT is blocked. In contrast to the two-level VSC-HVDC system under the PPF, in which a IGBT from overcurrent damage. The voltage cross converter unit 𝑣 decreases with SM capacitor large capacitor connected to the DC side discharges to zero, even if IGBT is blocked (assuming the discharging until the IGBT is blocked. In contrast to the two-level VSC-HVDC system under the PPF, resistance in fault circuit R < 2 L /C ), the voltage of the SM capacitor is normally maintained eq eq eq in which a large capacitor connected to the DC side discharges to zero, even if IGBT is blocked given the blocked IGBTs in the MMC-HVDC system. If v is higher than the AC grid line voltage conv (assuming the resistance in fault circuit 𝑅 <2 𝐿 /𝐶 ), the voltage of the SM capacitor is v (j indicates phases a, b, and c), then the AC grid current cannot be fed in the fault current loop. s j_line normally maintained given the blocked IGBTs in the MMC-HVDC system. If 𝑣 is higher than the If V is lower than the AC grid line voltage, then the AC grid begins to feed the AC current i (j conv s j AC grid line voltage 𝑣 (j indicates phases a, b, and c), then the AC grid current cannot be fed in indicates phases a, b, and c) into the fault current loop. In Figure 3, the red dashed line indicates the the fault current loop. If 𝑉 is lower than the AC grid line voltage, then the AC grid begins to feed the AC current 𝑖 (j indicates phases a, b, and c) into the fault current loop. In Figure 3, the red Appl. Sci. 2019, 9, x 6 of 26 Appl. Sci. 2019, 9, x 6 of 26 Appl. Sci. 2019, 9, 1661 6 of 26 dashed line indicates the fault currents 𝑖 fed from the AC grid; these fault currents are equally dashed line indicates the fault currents 𝑖 fed from the AC grid; these fault currents are equally divided into an upper arm current 𝑖 and a lower arm current 𝑖 (not marked in the figure fault currents i fed from the AC grid; these fault currents are equally divided into an upper arm divided into an upper arm current 𝑖 _ and a lower arm current 𝑖 _ (not marked in the figure s j _ _ due to complexity). The blue dashed–dotted line represents the capacitor discharging path, and 𝑖 current i and a lower arm current i (not marked in the ﬁgure due to complexity). The blue due to complexity). The blue dashed–dotted line represents the capacitor discharging path, and 𝑖 p j_ac n j_ac dashed–dotted expresses the disch line r aepr rging esents arm cur the capacitor rents. Both AC dischar fee ging dingpath, current in and i red expr and esses SM c the apac dischar itor diging scharg arm ing expresses the discharging arm currents. Both AC feeding current in red c j and SM capacitor discharging current in blue flow through inserted SMs and removed SMs in each arm. Specifically, the fault currents. Both AC feeding current in red and SM capacitor discharging current in blue ﬂow through current in blue flow through inserted SMs and removed SMs in each arm. Specifically, the fault inserted current flow SMs and s through removed fre SMs ewheeling in each diode in remo arm. Speciﬁcally ved SMs and , the fault curr cap enta ﬂows citor an thrd ough on-state freewheeling IGBT in current flows through freewheeling diode in removed SMs and capacitor and on-state IGBT in inserted SMs, shown in Figure 3. The equivalent circuits of the two fault current paths are exhibited diode in removed SMs and capacitor and on-state IGBT in inserted SMs, shown in Figure 3. The inserted SMs, shown in Figure 3. The equivalent circuits of the two fault current paths are exhibited in Figure 4a,b. However, the AC feeding current can be ignored in comparison with the capacitor equivalent circuits of the two fault current paths are exhibited in Figure 4a,b. However, the AC feeding in Figure 4a,b. However, the AC feeding current can be ignored in comparison with the capacitor discharging current during this period. current can be ignored in comparison with the capacitor discharging current during this period. discharging current during this period. Phase-B Phase-C i i i pa Phase-B Phase-C T i A pa pb i pc i T A 1 D pb pc upper arm upper arm i dc1 Inserted 1 D C 1 upper arm upper arm dc1 Inserted 1 C 0 SMs SMs T T i i i 2 D 2 i ca i cb i cc D 2 ca cb cc v 2 conv conv 1 D Removed D 1 Removed SMs SMs T 2 D 2 2 C uv > uv sa _ line> convL L L Pole-to- sa sa _ line conv L L L Pole-to- sa 0 0 L 0 0 0 pole Fault uv > L i i i pole Fault uv sb _ line> conv L sb sa i i na sb sa sb _ line conv sb na sb i i uv > L i nb i sc uv sc _ line> conv L sc nb sc sc _ line conv sc nc nc L 0 L 0 0 Phase-A Phase-B Phase-C Phase-A Phase-B Phase-C lower arm lower arm lower arm lower arm lower arm lower arm Figure 3. Direct current pole-to-pole fault circuit diagram before blocking submodules Figure 3. Direct current pole-to-pole fault circuit diagram before blocking submodules Figure 3. Direct current pole-to-pole fault circuit diagram before blocking submodules. i pa _ ac L R pa _ ac u L R L dc R dc C i i dis u L R dc dc sa sa sa C eq i sa dis sa sa sa sa eq i i L 0 i na _ ac i dis 0 i i i na _ ac R dis L i i i ca cb cc R dc L dc ca cb cc dc dc − + i + pb _ ac pb _ ac I + u L R i + C C I u sb L sb R sb C dis0 i sb sb sb sb C eqa C eqb C eqc dis0 sb i R L eqa eqb eqc i nb _ ac R L 0 eq nb _ ac R R 0 eq R fault R fault − fault fault − L R 2 L i pc _ ac 2 L 2 L L dc R dc − + pc _ ac 2 L 2 L 2 L 0 dc dc 0 0 − + u L R i 0 0 0 L sc i sc u sc R sc sc sc sc sc L R L dc R dc L i L dc dc eq i nc _ ac L 0 nc _ ac 0 eq (a) (b) (c) (a) (b) (c) Figure 4. (a) Equivalent AC grid feeding current circuit, (b) equivalent SM capacitor discharging Figure 4. (a) Equivalent AC grid feeding current circuit, (b) equivalent SM capacitor discharging Figure 4. (a) Equivalent AC grid feeding current circuit, (b) equivalent SM capacitor discharging current circuit, (c) simplified SM capacitor discharging current circuit. current circuit, (c) simpliﬁed SM capacitor discharging current circuit. current circuit, (c) simplified SM capacitor discharging current circuit. 2C The equivalent phase capacitor C demonstrated in Figure 4b is normally considered in the eq existing references [5,6,15,17]. However, Referπ ence [36] proposed that the calculation value of the 4.42 （， 4.4194） 4.42 C （， 4.4194） 1.4 C 0 0 fault current with C = is close to the simulation value. Furthermore, C is obtained as for eq eq N N the optimal approximation of the discharging current via a tracing point method [37]. Consequently, 4.4 4.4 Reference [38] veriﬁed that C of the three converter units depends on the fault time t and modulation eq f ratio m, as expressed in Equation (1). Thus, the selection of fault time t and modulation ratio m should 4.38 4.38 be reconsidered in this paper. Based on equivalent capacitor expression in Equation (2), the relationship between discharging coecient and time is shown in Figure 5, given the preset modulation ratio 4.36 4.36 （， 4.3536）（， 4.3536） m (0.93) of test system. From the perspective of fault protection, the most serious situation must be considered in selecting t . According to the red curve in Figure 5, the maximum discharging coecient 4.34 4.34 0 k 0.002 0.004 0.006 0.008 0.01 0 0.002 0.004 0.006 0.008 0.01 is obtained when t = , k = 0, 1, 2:::. Namely, the maximum C equals 1.473, since the fault time eq Time(s) Time/s Ti Tim me e(/s s) of the simulation is set at 1.2 s. Figure 5. Relationship between discharging coefficient and fault time (m = 0.93). Figure 5. Relationship between discharging coefficient and fault time (m = 0.93). 2C 2C 2C 0 0 0 C = + + (1) eq 2 2 2 2 2 2 2 2 [1 + m sin (!t)]N [1 + m sin (!t )]N [1 + m sin (!t + )]N 3 3 Discharging coefficient Discharging coefficient Appl. Sci. 2019, 9, x 6 of 26 dashed line indicates the fault currents 𝑖 fed from the AC grid; these fault currents are equally divided into an upper arm current 𝑖 and a lower arm current 𝑖 (not marked in the figure _ _ due to complexity). The blue dashed–dotted line represents the capacitor discharging path, and 𝑖 expresses the discharging arm currents. Both AC feeding current in red and SM capacitor discharging current in blue flow through inserted SMs and removed SMs in each arm. Specifically, the fault current flows through freewheeling diode in removed SMs and capacitor and on-state IGBT in inserted SMs, shown in Figure 3. The equivalent circuits of the two fault current paths are exhibited in Figure 4a,b. However, the AC feeding current can be ignored in comparison with the capacitor discharging current during this period. Phase-B Phase-C pa i T A pb pc i 1 D upper arm upper arm dc1 Inserted 1 C SMs 2 i i i ca cb cc v 2 conv Removed 1 SMs 2 C uv > L L Pole-to- sa _ line conv sa L 0 0 pole Fault uv > L i i i sb _ line conv sb sa na sb i i uv > L nb sc sc _ line conv sc nc L L 0 0 Phase-A Phase-C Phase-B lower arm lower arm lower arm Figure 3. Direct current pole-to-pole fault circuit diagram before blocking submodules pa _ ac L R u L dc dc C i dis sa sa sa sa eq na _ ac i i i dis L ca cb cc dc dc pb _ ac I + u L R sb sb C C C dis0 sb sb eqa eqb eqc i R nb _ ac eq R R fault fault − L R pc _ ac 2 L 2 L 2 L − + dc dc 0 0 0 L i u R sc sc sc sc L R dc dc L i L nc _ ac 0 eq Appl. Sci. 2019, 9, 1661 7 of 26 (a) (b) (c) Figure 4. (a) Equivalent AC grid feeding current circuit, (b) equivalent SM capacitor discharging C = (2) eq current circuit, (c) simplified SM capacitor discharging current circuit. 4.42 （， 4.4194） 4.4 4.38 4.36 （， 4.3536） 4.34 0 0.002 0.004 0.006 0.008 0.01 Ti Tim me e(/s s) Figure Figure 5. 5. Relationship Relationship betwee betweenn dis dischar charg ging ing coe coe fficient and f cient and fault ault time (m = time (m = 0.93). 0.93). During the SM capacitor discharging period, the AC feeding current can be ignored, because the discharging current is dominant. For example, the Phase-A discharging circuit can be regarded as a second-order RLC circuit (circuit consisting of a resistor, an inductor and a capacitor), as displayed in Figure 4c. Here, the resistance in the arms is neglected. The initial voltage and current of the capacitor discharging circuit are expressed by Equations (3) and (4), respectively. u (0 ) = u (0 ) = U (3) c + c dc du i (0 ) = i (0 ) = C = I (4) dis + dis eq dis0 dt The equivalent capacitor, inductance, and resistance presented in Figure 4c are obtained as follows: C = (5) eq L = L + 2L (6) eq 0 dc R = R + 2R (7) eq f ault dc The second-order equation of the RLC circuit is expressed in Equation (8) as follows: d i eq di 1 dis dis + + i = 0 (8) dis dt L dt L C eq eq eq t eq I ! dis0 0 i (t) = e [U sin(! t) sin(! t )] (9) dis dc 1 1 L ! eq 1 2L 2( L + 2L ) eq 0 dc = = (10) R 2R + R eq dc f ault 1 eq ! = (11) L C 2L eq eq eq ! = (12) L C eq eq = arctan(!) (13) Discharging coefficient Appl. Sci. 2019, 9, 1661 8 of 26 where is the attenuation coecient of the capacitor discharging current, ! is the oscillating current angular frequency, ! is the inherent angular frequency of the circuit, and is the initial phase angle of the initial current. The capacitor discharges until the capacitor voltage decreases to 0. The maximum discharging current can be obtained at t without blocking IGBT. dis_peak 1 U eq dc t = arctan( ) (14) dis_peak ! I L 0 dis0 eq dis_peak C I ! L eq 0 eq dis0 dc I = e (U + ) (15) dis_peak dc 2 2 2 2 L U eq I ! L + U dc eq dis0 dc The AC side can be considered a three-phase short-circuit fault under the DC pole-to-pole fault, and the DC fault current only consists of the discharging currents of the three converter units, given the balance fault on the AC side. Thus, the fault current through DC line is deﬁned as i (t) = i (t) (16) dc dis For example, Phase-A arm current during this period can be decomposed using Equations (17) and (18). 1 1 i (t) = i (t) + i (t) (17) pa sa dc 3 2 1 1 i (t) = i (t) i (t) (18) na dc sa 3 2 The Phase-A voltage on the AC side is set as u = 2U sin(! t + ) (19) sa s s a where is the phase angle (taken as 0 for convenience in calculation afterward), and ! is the a s fundamental angular frequency. Then, the Phase-A current can be obtained using Equation (20). 2U i = sin(! t + ') (20) sa s a eq where ' is the impedance angle. The AC feeding current in each phase is equally divided into upper and lower arms. 1 2U i (t) = i (t) = sin(! t + ') (21) pa_ac na_ac s a 2 Z eq Z = R + ! L + L (22) eq s s 0 sa L + L sa 0 '= arctan( ) (23) sa In accordance with Equations (9), (16)–(18), and (21), the expression of the Phase-A arm current can be obtained. 1 t eq I ! 1 2U dis0 0 s i = e [U sin(! t) sin(! t )] + sin(! t + ') (24) pa s a dc 1 1 3 L ! 2 Z eq eq t I ! 1 eq 1 2U 0 s dis0 i = e [U sin(! t) sin(! t )] sin(! t + ') (25) na dc 1 1 s a 3 L ! 2 Z eq 1 eq Appl. Sci. 2019, 9, 1661 9 of 26 2.2.2. Freewheeling Current and AC Feeding Current Period Appl. Sci. 2019, 9, x 9 of 26 The fault current circuit after completely discharging IGBT blocks or capacitor to V = 0 is conv Appl. Sci. 2019, 9, x 9 of 26 depicted in Figure 6, in which the red dotted line indicates the AC feeding current, and the blue dash-dotted line represents the freewheeling current given 1 the stored energy in the arm reactors. The LL + sa 0 equivalent circuits of the AC feeding and freewheeling DC currents are illustrated in Figure 7a,b, 2 (23) ϕ =arctan( ) LL + sa 0 respectively. The fault current can be considered a superposition of the three-phase short-circuit fault sa 2 (23) ϕ =arctan( ) and decayed freewheeling currents. Thus, the fault currents in the upper and lower arms can be sa In accordance with Equations (9), (16)–(18), and (21), the expression of the Phase-A arm current deﬁned as can be obtained. In accordance with Equations (9), (16)–(18), and (21), the expression of the Phase-A arm current i = i + i (26) p j p j_ac f w j can be obtained. 11IU ω 2 eq dis00 s i = i i (27) ie=− [U sin(ωω t) sin( t−θ )]+ sin(ωt+θ− ϕ ) n j f w j n j_ac (24) pa dc 11 sa 32 −LZ C ω 11IU ω 2 eq 1 eq eq dis00 s ie=− [U sin(ωω t) sin( t−θ )]+ sin(ωt+θ− ϕ ) (24) pa dc 11 sa where i denotes the freewheeling current in each converter phase. i and i indicate the AC f w j p j_ac n j_ac 32LZ ω eq 1 eq feeding current via the upper and lower arms of each phase, respectively. The analysis during the SM − C 11IU ω 2 eq dis00 s capacitor discharging period shows that the initial freewheeling current is equal to the peak value of ie=− [U sin(ωω t ) sin( t−θ )]− sin(ωt+θ− ϕ ) (25) na dc 11 sa 32LZ C ω 11IU ω 2 eqeq 1 eq dis00 s the discharging current in each converter phase. ie=− [U sin(ωω t ) sin( t−θ )]− sin(ωt+θ− ϕ ) (25) na dc 11 sa 32LZ ω eq 1 eq I = I (28) 2.2.2. Freewheeling Current and AC Feeding C f w0urrent dis Period _peak 2.2.2. Freewheeling Current and AC Feeding Current Period i T Phase-B Phase-C pb pa 1 D A pc C dc 2 upper arm upper arm i T Phase-B Phase-C D pb A pa 1 i pc T 1 C upper arm dc 2 D upper arm 2 0 i v fwb fwc fwa Blocked conv 2 i i T i SMs fwc v 1 fwb D fwa conv Blocked SMs 1 D 2 C uv > L D 2 C L L Pole-to- sa _ line conv sa 2 L 0 0 pole Fault uv > uv > LL sa _ line conv L L Pole-to- sa sb _ line conv sb sa L 0 0 pole Fault uv > L i i uv > L i i sb _ line conv sb sc _ line conv sc sa na sb nb nc uv > L i i i i L na L sc _ line conv sc sb nb sc nc sc 0 0 Phase-A Phase-B Phase-C lower arm lower arm lower arm Phase-A Phase-B Phase-C lower arm lower arm lower arm Figure 6. Diagram of the DC pole-to-pole fault circuit after blocking SMs. Figure 6. Diagram of the DC pole-to-pole fault circuit after blocking SMs. Figure 6. Diagram of the DC pole-to-pole fault circuit after blocking SMs. pa _ ac i L R u L R fw dc dc sa sa sa sa i L pa _ ac 0 na _ ac i i L R i i R fwc u L R L fwa fwb i fw dc dc dc sa sa sa dc sa pb _ ac 0 na _ ac i i i u L R i R I fwa I I fwc L fwb sb sb sb sb dc fw 0 fw 0 fw 0 dc i i nb pb _ a _cac R fault u L R fault i I I I sb sb sb fw 0 fw 0 fw 0 sb i L nb _ ac L R 2L R pc _ ac 0 2L 2L dc dc R 0 0 0 fault u L R i fault sc sc sc sc L R L R 2L dc i L 2L 2L dc pc _ ac dc dc nc _ ac 0 0 0 0 L i u R sc sc sc sc dc dc i L nc _ ac (a) (b) (a) (b) Figure 7. Equivalent circuit of the (a) AC feeding current and (b) freewheeling DC current. Figure 7. Equivalent circuit of the (a) AC feeding current and (b) freewheeling DC current. Figure 7. Equivalent circuit of the (a) AC feeding current and (b) freewheeling DC current. The fault current circuit after completely discharging IGBT blocks or capacitor to 𝑉 =0 is depicted in Figure 6, in which the red dotted line indicates the AC feeding current, and the blue dash- The fault current circuit after completely discharging IGBT blocks or capacitor to 𝑉 =0 is dotted line represents the freewheeling current given the stored energy in the arm reactors. The depicted in Figure 6, in which the red dotted line indicates the AC feeding current, and the blue dash- equivalent circuits of the AC feeding and freewheeling DC currents are illustrated in Figure 7a and dotted line represents the freewheeling current given the stored energy in the arm reactors. The Figure 7b, respectively. The fault current can be considered a superposition of the three-phase short- equivalent circuits of the AC feeding and freewheeling DC currents are illustrated in Figure 7a and Figure 7b, respectively. The fault current can be considered a superposition of the three-phase short- Appl. Sci. 2019, 9, 1661 10 of 26 Thus, the freewheeling current of each arm and the DC line current can be obtained using Equations (29) and (30). i (t) = I e (29) f w j f w0 i (t) = 3I e (30) dc f w0 For example, the initial arm current of the freewheeling period of Phase A is expressed as follows: I = I + i (t ) (31) pa_bk f w0 sa dis_peak I = I i (t ) (32) sa na_bk f w0 dis_peak Similarly, the arm currents can be decomposed as Equations (33) and (34). i (t) = i (t) + i (t) (33) pa f wa pa_ac i (t) = i (t) i (t) (34) na f wa na_ac In reference to Equations (21) and (28), the arm currents can be deﬁned as 1 1 2U i (t) = I e + sin(! t + ') (35) pa dis_peak s a 3 2 Z eq 1 1 2U i (t) = I e sin(! t + ') (36) na dis_peak s a 3 2 Z eq 2(2L +2L ) 0 dc = (37) 2R + R dc f ault where is the attenuation coecient of the freewheeling current. Equivalent impedance is expressed in Equation (22), and the peak value of the discharging current can be obtained via Equation (15). 2.3. Simulation Veriﬁcation The analyses of the arm and DC line currents have been veriﬁed via a simulation. The monopolar MMC-HVDC system is adopted in this study, and the model parameters are listed in Table 1. The rectiﬁer side takes DC voltage and active power control, and the inverter side adopts active and reactive power controls. The protection action, including blocking IGBTs, is disregarded in the simulation to investigate the natural response to a fault. A completely discharged SM capacitor can be equivalent to blocking IGBTs at t . The comparison between the calculation and the simulation in terms of dis_peak DC line and arm currents (Phase-A upper arm) is depicted in Figures 8 and 9, respectively. Figure 8 demonstrated that the DC line current increases to a high level in a few milliseconds. The IGBTs must be blocked rapidly due to the electrical pressure on the DC line. The DC line current decays after completely discharging the SM capacitor. Similarly, the arm current accelerates during the discharging period (Figure 9) but involves the AC feeding component after completely discharging the SM capacitor at 1.213 s. The dierence between the simulation and calculation values in the arm current before 1.213 s may be attributed to the imbalance shunt current among the converter units. In addition, the initial AC current at fault time (1.2 s) is ignored in the calculation, thereby leading to more or less error. However, the overall accuracy of the calculation analysis can be accepted for fault study on the basis of the general consistency between the simulation and calculation curves in Figures 8 and 9. Appl. Sci. 2019, 9, x 11 of 26 Appl. Sci. 2019, 9, x 11 of 26 rectifier side takes DC voltage and active power control, and the inverter side adopts active and rectifier side takes DC voltage and active power control, and the inverter side adopts active and reactive power controls. The protection action, including blocking IGBTs, is disregarded in the reactive power controls. The protection action, including blocking IGBTs, is disregarded in the simulation to investigate the natural response to a fault. A completely discharged SM capacitor can simulation to investigate the natural response to a fault. A completely discharged SM capacitor can be equivalent to blocking IGBTs at 𝑡 . The comparison between the calculation and the be equivalent to blocking IGBTs at 𝑡 _ . The comparison between the calculation and the simulation in terms of DC line and arm currents (Phase-A upper arm) is depicted in Figure 8 and 9, simulation in terms of DC line and arm currents (Phase-A upper arm) is depicted in Figure 8 and 9, respectively. Figure 8 demonstrated that the DC line current increases to a high level in a few respectively. Figure 8 demonstrated that the DC line current increases to a high level in a few milliseconds. The IGBTs must be blocked rapidly due to the electrical pressure on the DC line. The milliseconds. The IGBTs must be blocked rapidly due to the electrical pressure on the DC line. The DC line current decays after completely discharging the SM capacitor. Similarly, the arm current DC line current decays after completely discharging the SM capacitor. Similarly, the arm current accelerates during the discharging period (Figure 9) but involves the AC feeding component after accelerates during the discharging period (Figure 9) but involves the AC feeding component after completely discharging the SM capacitor at 1.213 s. The difference between the simulation and completely discharging the SM capacitor at 1.213 s. The difference between the simulation and calculation values in the arm current before 1.213 s may be attributed to the imbalance shunt current calculation values in the arm current before 1.213 s may be attributed to the imbalance shunt current among the converter units. In addition, the initial AC current at fault time (1.2 s) is ignored in the among the converter units. In addition, the initial AC current at fault time (1.2 s) is ignored in the calculation, thereby leading to more or less error. However, the overall accuracy of the calculation calculation, thereby leading to more or less error. However, the overall accuracy of the calculation analysis can be accepted for fault study on the basis of the general consistency between the simulation analysis can be accepted for fault study on the basis of the general consistency between the simulation and calculation curves in Figure 8 and 9. and calculation curves in Figure 8 and 9. Appl. Sci. 2019, 9, 1661 11 of 26 Table 1. Parameters of the modular multilevel converter-based high-voltage direct current system’s Table 1. Parameters of the modular multilevel converter-based high-voltage direct current system’s Table 1. Parameters of the modular multilevel converter-based high-voltage direct current system’s simulation model. simulation model. simulation model. System Parameters System Parameters System Parameters DC voltage ± 420 kV SM number (2 N) 60 DC voltage ± 420 kV SM number (2 N) 60 Rated power 1250 MW Arm inductance 140 mH DC voltage 420 kV SM number (2 N) 60 Rated power 1250 MW Arm inductance 140 mH Rated power 1250 MW Arm inductance 140 mH Short-circuit ratio 20 Internal grounding Yg Short-circuit ratio 20 Internal grounding Yg Short-circuit ratio 20 Internal grounding Yg AC voltage 450 kV AC line length 10 km AC voltage 450 kV AC line length 10 km AC voltage 450 kV AC line length 10 km Frequency 50 Hz Line resistance 12.73m/ Ω km Frequency 50 Hz Line resistance 12.73m/ Ω km Frequency 50 Hz Line resistance 12.73 mW/km Transformer voltage 525 kV/450 kV Line inductance 0.9937 mH T Trans ransformer formevoltage r voltage 525 525 kV/ kV/450 45kV 0 kV Line Line induct inductance ance 0.9937 0.9937 mH mH TTransformer ransformer grounding grounding Yn Yn/yn /yn Line Line c capacitance apacitance 12.74 12.74 n nF/km F/km Transformer grounding Yn/yn Line capacitance 12.74 nF/km Smoothing inductance 20 mH DC line length 200 km Smoothing inductance 20 mH DC line length 200 km Smoothing inductance 20 mH DC line length 200 km x 10 x 10 simulation value simulation value calculation value(discharging) calculation value(discharging) calculation value(freewheeling) calculation value(freewheeling) ts = 1.213 ts dis _ peak= 1.213 dis _ peak 1.2 1.22 1.24 1.26 1.28 1.3 1.2 1.22 1.24 1.26 1.28 1.3 Ti Tim me e( /s s) Time/s Time(s) Figure 8. Simulation and calculation values of the DC line current. Figure Figure 8. 8. Sim Simulation ulation an and d cal calculation culation va values lues o of f th the e DC DC l line ine cu curr rren ent. t. x 10 x 10 calculation value(discharging) calculation value(discharging) calculation value(freewheeeling+AC feeding) calculation value(freewheeeling+AC feeding) simulation value 1.5 simulation value 1.5 0.5 0.5 ts = 1.213 ts dis _ peak= 1.213 dis _ peak 1.2 1.22 1.24 1.26 1.28 1.3 1.2 1.22 1.24 1.26 1.28 1.3 Ti Time(s me/s) Ti Time(s me/s) Figure Figure 9. 9. Simulation Simulationand andcalculation calculation v values aluesof of the the arm current (Phase-A upper arm). arm current (Phase-A upper arm). Figure 9. Simulation and calculation values of the arm current (Phase-A upper arm). 2.4. Protection Demand The MMC-HVDC system focuses on the protection and healthy part safety of the converter station. Speciﬁcally, the IGBTs are regarded as important components in the converter station given their high cost but low electrical withstanding ability. IGBTs and freewheeling diodes are destroyed due to overheating under extremely high arm current. Another point in protection relaying is that the DCCB occupies a large portion of the cost in the HVDC project considering its high interruption capacity. Therefore, the arm and DC line currents under a fault must be investigated, and the limitation of fault current methods is required to satisfy protection demands. In accordance with the fault current analysis discussed in Section 2, the anti-parallel diodes in removed SMs and IGBTs in inserted SMs experience a dramatic overcurrent before blocking IGBTs. Moreover, the diode D in inserted SMs can withstand the peak value of the discharging current when the IGBTs T are blocked; this issue is considered an essential challenge to the DC fault protection of the MMC-HVDC system [4]. Considering the action of blocking IGBTs, the arm current under the DC pole-to-pole fault has been simulated (Figure 10). Using Equations (16) and (28), the DC current reaches 30 kA when the Phase- A Ar m uppe curr r ar enm c t(Au ) rrent/A Phase- A Ar m uppe curr r ar enm c t(Au ) rrent/A DC Current(A) DC current/A DC Current(A) DC current/A Appl. Sci. 2019, 9, x 12 of 26 2.4. Protection Demand The MMC-HVDC system focuses on the protection and healthy part safety of the converter station. Specifically, the IGBTs are regarded as important components in the converter station given their high cost but low electrical withstanding ability. IGBTs and freewheeling diodes are destroyed due to overheating under extremely high arm current. Another point in protection relaying is that the DCCB occupies a large portion of the cost in the HVDC project considering its high interruption capacity. Therefore, the arm and DC line currents under a fault must be investigated, and the limitation of fault current methods is required to satisfy protection demands. In accordance with the fault current analysis discussed in Section 2, the anti-parallel diodes in removed SMs and IGBTs in inserted SMs experience a dramatic overcurrent before blocking IGBTs. Moreover, the diode 𝐷 in inserted SMs can withstand the peak value of the discharging current when the IGBTs 𝑇 are blocked; this issue is considered an essential challenge to the DC fault protection of the MMC-HVDC system [4]. Considering the action of blocking IGBTs, the arm current under the DC pole-to-pole fault has Appl. Sci. 2019, 9, 1661 12 of 26 been simulated (Figure 10). Using Equations (16) and (28), the DC current reaches 30 kA when the IGBT is blocked beyond the maximum interruption capacity of 16 kA [33]. When a fault occurs, the arm current mainly consists of the capacitor discharging and AC feeding currents in the initial stage. IGBT is blocked beyond the maximum interruption capacity of 16 kA [33]. When a fault occurs, the Specifically, the SM capacitor begins to discharge the current through arms and DC loops, and the arm current mainly consists of the capacitor discharging and AC feeding currents in the initial stage. IGBTs are blocked with a triggering signal while the arm current reaches the threshold value. The Speciﬁcally, the SM capacitor begins to discharge the current through arms and DC loops, and the IGBT blocking time is set to 1.205 s, that is, 5 ms after fault occurrence to provide a distinguishable IGBTs are blocked with a triggering signal while the arm current reaches the threshold value. The IGBT vision on the current development; this timeframe is slightly longer than that in the real project (2– blocking time is set to 1.205 s, that is, 5 ms after fault occurrence to provide a distinguishable vision on 3ms). In addition, the AC side begins to feed current into the fault current circuit while a fault occurs the current development; this timeframe is slightly longer than that in the real project (2–3 ms). In because the rated AC line voltage is set to more than half of the DC voltage (𝑉 = 450𝑘𝑉, 𝑉 = addition, the AC side begins to feed current into the fault current circuit while a fault occurs because ±420𝑘𝑉 ). However, if 𝑉 < 𝑉 =0.5𝑈 , then the AC feeding current will appear as 𝑉 > _ _ the rated AC line voltage is set to more than half of the DC voltage (V = 450 kV, V = 420 kV). AC_line DC 𝑉 given the SM capacitor’s discharging effect. In Figure 10, the AC feed current (red line) in the However, if V < V = 0.5U , then the AC feeding current will appear as V > V given DC DC DC AC_line AC_line three-phase uncontrolled rectifier bridge, and the energy stored in the arm reactors begin to freewheel the SM capacitor ’s discharging eect. In Figure 10, the AC feed current (red line) in the three-phase decayed current (blue line) through anti-parallel diodes because the IGBTs are blocked. The AC uncontrolled rectiﬁer bridge, and the energy stored in the arm reactors begin to freewheel decayed circuit breaker (ACCB) is triggered to isolate the fault section after a fault is detected. The delay in current (blue line) through anti-parallel diodes because the IGBTs are blocked. The AC circuit breaker the ACCB is normally 4–5 cycles. Thus, the triggering time point is set to 100 ms after the fault (ACCB) is triggered to isolate the fault section after a fault is detected. The delay in the ACCB is occurrence. Figure 10 demonstrates that the arm current reaches approximately 10 kA while the IGBT normally 4–5 cycles. Thus, the triggering time point is set to 100 ms after the fault occurrence. Figure 10 blocks and decays slowly with the AC feeding component. The limitation of the fault current is demonstrates that the arm current reaches approximately 10 kA while the IGBT blocks and decays essential to realize protection considering the limitation in the DCCB capability. The AC feeding slowly with the AC feeding component. The limitation of the fault current is essential to realize current can be restrained using a parallel-connected thyristor in previous works [18–21]. Therefore, protection considering the limitation in the DCCB capability. The AC feeding current can be restrained the discharging current limitation and rapid decaying freewheeling current are the focus in the using a parallel-connected thyristor in previous works [18–21]. Therefore, the discharging current present study. limitation and rapid decaying freewheeling current are the focus in the present study. AC feeding current Capacitor discharging current & reactor freewheeling current Arm current (phase-A upper arm) -2000 Fault occurence IGBT blocked（1.205s) ACCB triggered -4000 1.18 1.2 1.22 1.24 1.26 1.28 1.3 1.32 Time(s) Figure 10. Phase-A upper arm current under the DC pole-to-pole fault. Figure 10. Phase-A upper arm current under the DC pole-to-pole fault. 3. Enhanced Fault Current Limiting Circuit 3. Enhanced Fault Current Limiting Circuit 3.1. Fault Current-Limiting Characteristics 3.1. Fault Current-Limiting Characteristics The FCLC mainly consists of energy dissipation resistance and limiting inductance [14,15,25,35]. Thus, investigating the inﬂuence of the two elements on the fault current development is important. The related simulation was performed under controlled conditions. Figure 11a displays that limiting inductance can help slow down the accelerating speed of the fault current but increase the time spent in decaying the freewheeling current to its expected level. In Figure 11b, the energy dissipation resistance facilitates the constraining fault current peak value and the accelerating extinguishment of the freewheeling current. The adoption of the reactor and resistance in the discharging period is suitable, considering that the maximum fault current will ﬂow through the freewheeling diode while the IGBTs are blocked or the SM capacitors are completely discharged. However, the limiting inductance can aect the dynamic response speed and prolong the recovery time. Therefore, further study on the FCLC design is required. A series of simulations was conducted under controlled conditions to obtain the expected fault current limitation and rapid recovery. The simulation conditions are divided into resistance and reactor groups as follows: the former is labeled with “a”, “b”, “c”, and “d”, and the latter with “e”, “f”, “g”, and “h”. Speciﬁcally, the related explanations of the conditions are listed in Table 2. “X” indicates that Arm current(A) Appl. Sci. 2019, 9, 1661 13 of 26 Appl. Sci. 2019, 9, x 13 of 26 the resistance or reactor is inserted in the fault circuit, and “” denotes the absence of resistance or The FCLC mainly consists of energy dissipation resistance and limiting inductance [14,15,25,35]. reactor. First, the reactor was ignored, and Figure 12a illustrates that the red curve (“ag”) provides an Thus, investigating the influence of the two elements on the fault current development is important. improved performance in limiting fault current. Thus, the condition with “a” was selected for the The related simulation was performed under controlled conditions. Figure 11a displays that limiting following simulation. Figure 12b depicts the performance of various reactor-based FCLC scheme, in inductance can help slow down the accelerating speed of the fault current but increase the time spent which the red dashed–dotted curve (“ad”) represents the lowest fault current level. However, the “ad” in decaying the freewheeling current to its expected level. In Figure 11b, the energy dissipation scheme was unsatisfactory for real projects, where large inductance will aect the dynamic response resistance facilitates the constraining fault current peak value and the accelerating extinguishment of speed of the entire system during the normal state. Therefore, the “af” scheme most closely approaches the freewheeling current. The adoption of the reactor and resistance in the discharging period is the optimized FCLC scheme, because the energy dissipation resistance consumes the energy in the suitable, considering that the maximum fault current will flow through the freewheeling diode while Appl. Sci. 2019, 9, x 13 of 26 fault circuit. This phenomenon is due to the fault being detected, and the FCL reactor being inserted to the IGBTs are blocked or the SM capacitors are completely discharged. However, the limiting limit the increase in current speed, but also being removed to accelerate the decaying speed of the inductance can affect the dynamic response speed and prolong the recovery time. Therefore, further The FCLC mainly consists of energy dissipation resistance and limiting inductance [14,15,25,35]. study on freewheeling the FCLC des current i after gn is r blocking equired. the IGBT. Thus, investigating the influence of the two elements on the fault current development is important. The related simulation was performed under controlled conditions. Figu 4 re 11a displays that limiting 4 x 10 x 10 inductance can help slow down the accelerating speed of the fault current but increaNon se the ti e me spent None 6 L=20mH R=0.05ohm in decaying the freewheeling current to its expected level. In Figure 11b, the energy dissipation R=0.05ohm L=20mH R=0.05ohm L=20mH 5 R=0.5ohm L=20mH R=0.05ohm L=100mH resistance facilitates the constraining fault current peak value and the accelerating extinguishment of x 10 R=5ohm L=20mH 4 4 R=0.05ohm L=200mH the freewheeling current. The adoption of the reactor and resistance in the discharging period is 3 3 x 10 suitable, considering that the maximum fault current wil1l flow through the freewheeling diode while 2 2 1.2 1.205 the IGBTs 1 are blocked or the SM capacitors are completely discharged. However, the limiting 0 0 inductance can affect the dynamic response speed and prolong the recovery time. Therefore, further 1.2 1.205 Fault occurrence Fault occurrence -1 -1 study on 1.1 the 1.2 FCLC des 1.3 1.i 4gn is r 1.5 equir 1.6 ed. 1.7 1 1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8 Time(s) Time(s) 4 x 10 x 10 (a) ( b) None None 6 L=20mH R=0.05ohm Figure 11. DC fault current characteristics (a) with variable limiting inductance; (b) with variable Figure 11. DC fault current characteristics (a) with variable limiting inductance; (b) with R=0.05oh variable m L=20mH R=0.05ohm L=20mH 5 R=0.5ohm L=20mH R=0.05ohm L=100mH 4 energy dissipation resistance. energy dissipation resistance. x 10 R=5ohm L=20mH 4 4 R=0.05ohm L=200mH Table 4 2. Condition classiﬁcation for the fault current limiting circuit scheme. x 10 2 1 1.2 1.205 20000 1 Time Point Label Fault Occurred Fault Detected IGBT Blocked ad 0 ag 0 0 1.2 1.205 ae a X X Fault occurrence Fault occurrence bg af -1 Resistance-related -1 1.1 1.2 1.3 1.4 1.5 1.6 1.7 b X 1 1.1 ag 1.2 1.3 1.4 1.5 1.6 1.7 1.8 cg Time(s) condition ah Time(s) 5000 (a) ( d X X b) e X X Reactor-related Figure 11. 0 DC fault current characteristics (a) with variable limiting inductance; (b) with variable f X Fault 0 Fault condition Fault Fault occurrence IGBT blocked energy dissipation resi detected stance. IGBT blocked g oc currence detected -5000 -1000 1.199 1.2 1.201 1.202 1.203 1.204 1.205 1.199 1.2 1.201 1.202 1.203 1.204 1.205 h X X X Time(s) Time(s) (a) (b) ad ag ae Figure 12. Comparison among different FCL schemes (a) different resistance conditions without bg af ag considering the reactor, cg (b) different reactor conditions with selected resistance schemes. 3000 ah 5000 Table 2. Condition classification for the fault current limiting circuit scheme. Fault Fault IGBT Fault Fault 0 Time Point Label Fault Fault occurrence detected IGBT blocked Occurred Detected Blocke IGd BT blocked occurrence detected -5000 -1000 1.199 1.2 1.201 1.202 1.203 1.204 1.205 1.199 1.2 1.201 1.202 1.203 1.204 1.205 a ×   Resistance- Time(s) Time(s) related b ×  × (a) (b) condition c × × × Figure 12. Figure 12. Compari Comparison son among d d among di ifferent FCL erent FCL sschemes chemes (( aa) different res ) di er ent resistance istance cond conditions × iti ons withou without t consid considering ering the reactor, the reactor, ((b b)) d di ifferent reactor erent reactor conditions conditions wit with h sele selected cted resi resistance stance s schemes. chemes. e ×   Reactor- related f ×  × Table 2. Condition classification for the fault current limiting circuit scheme. condition g × × × h    Fault Fault IGBT Time Point Label Occurred Detected Blocked Resistance- a ×   related b ×  × condition c × × × d   × Reactor- e ×   related f ×  × condition g × × × h    DC Current(A) DC Current(A) DC Current(A) DC Current(A) DC Current(A) DC Current(A) DC Current(A) DC Current(A) Appl. Sci. 2019, 9, x 14 of 26 A series of simulations was conducted under controlled conditions to obtain the expected fault current limitation and rapid recovery. The simulation conditions are divided into resistance and reactor groups as follows: the former is labeled with “a”, “b”, “c”, and “d”, and the latter with “e”, “f”, “g”, and “h”. Specifically, the related explanations of the conditions are listed in Table 2. “” indicates that the resistance or reactor is inserted in the fault circuit, and “×” denotes the absence of Appl. Sci. 2019, 9, 1661 14 of 26 resistance or reactor. First, the reactor was ignored, and Figure 12a illustrates that the red curve (“ag”) provides an improved performance in limiting fault current. Thus, the condition with “a” was selected for the following simulation. Figure 12b depicts the performance of various reactor-based 3.2. Basic Topology FCLC scheme, in which the red dashed–dotted curve (“ad”) represents the lowest fault current level. The EFCLC is proposed on the basis of analyzing the fault current limitation characteristics However, the “ad” scheme was unsatisfactory for real projects, where large inductance will affect the (Figure 13). During the normal state, the series-connected IGBTs, namely, T and T , are opened. When 1 2 dynamic response speed of the entire system during the normal state. Therefore, the “af” scheme a fault is detected, T and T are closed by a switching-o signal, and the energy dissipation resistance 1 2 most closely approaches the optimized FCLC scheme, because the energy dissipation resistance R and FCL reactor L are inserted in the fault circuit. L will be bypassed via bidirectional FCL FCL FCL consumes the energy in the fault circuit. This phenomenon is due to the fault being detected, and the parallel-connected thyristors T and T . The surge arrestor is equipped to protect circuit components 3 4 FCL reactor being inserted to limit the increase in current speed, but also being removed to accelerate from surge current and voltage. In addition, the thyristors can function as a voltage stabilizer due to the decaying speed of the freewheeling current after blocking the IGBT. the surge voltage across L . Considering zero voltage switching and loss reduction, the IGBTs are FCL protected by a snubber circuit, which consists of snubber capacitor, snubber resistance, and diode [34]. 3.2. Basic Topology D D 1 2 T T 1 2 FCL R T FCL 3 MOA Figure 13. Proposed enhanced fault current limiting circuit. Figure 13. Proposed enhanced fault current limiting circuit. 3.3. Fault Current Interruption with DC Circuit Breaker The EFCLC is proposed on the basis of analyzing the fault current limitation characteristics (Figure 13). During the normal state, the series-connected IGBTs, namely, 𝑇 and 𝑇 , are opened. Considering that fault relay involves FCL behavior and DCCB operation, it is necessary to When a fault is detected, 𝑇 and 𝑇 are closed by a switching-off signal, and the energy dissipation investigate the coordination between EFCLC behavior and DCCB operation in this paper. Hence, resistance 𝑅 and FCL reactor 𝐿 are inserted in the fault circuit. 𝐿 will be bypassed via the fault interruption progress could be determined for further parameter setting of EFCLC. The bidirectional parallel-connected thyristors 𝑇 and 𝑇 . The surge arrestor is equipped to protect DCCB topologies in articles and patents can be classiﬁed into passive and active resonance DCCB, circuit components from surge current and voltage. In addition, the thyristors can function as a hybrid DCCB (HCB), and solid-state DCCB (SCB) [39]. The resonance-based DCCB spend a relatively voltage stabilizer due to the surge voltage across 𝐿 . Considering zero voltage switching and loss long time in fault current interruption and may lead to overcurrent. The HCB and SCB have a rapid reduction, the IGBTs are protected by a snubber circuit, which consists of snubber capacitor, snubber operation speed. Although the detailed topologies of the HCB and SCB are dierent from the nominal resistance, and diode [34]. path, these topologies can be equivalent to the ideal breaker in the nominal path and a metal oxide arrestor (MOA) when proactive switching control is applied [14,24]. A residential current breaker is 3.3 Fault Current Interruption with DC Circuit Breaker used to cut a residential current in the MOA, which is also modeled as an ideal breaker. The topologies of the DCCB and equivalent simulation model [14] are exhibited in Figure 14a,b, correspondingly. The Considering that fault relay involves FCL behavior and DCCB operation, it is necessary to main breaker demonstrated in Figure 14b will wait for the operation delay in ultrafast disconnector investigate the coordination between EFCLC behavior and DCCB operation in this paper. Hence, the switch (Figure 14a) operation, and the delay time is normally 2ms [33]. The fault current with a hybrid fault interruption progress could be determined for further parameter setting of EFCLC. The DCCB DCCB operation is exhibited in Figure 15. topologies in articles and patents can be classified into passive and active resonance DCCB, hybrid Figure 16 displays the fault current interruption sequence of the EFCLC with DCCB. T and T 1 2 DCCB (HCB), and solid-state DCCB (SCB) [39]. The resonance-based DCCB spend a relatively long are opened during the normal state, whereas T , T , and the DCCB main breaker are closed. When 3 4 time in fault current interruption and may lead to overcurrent. The HCB and SCB have a rapid a fault occurs, T and T remain open before a fault is detected, and the main breaker of the DCCB 1 2 operation speed. Although the detailed topologies of the HCB and SCB are different from the nominal remains closed (Figure 16a). When a fault is detected, T and T are switched o to insert an FCL 1 2 path, these topologies can be equivalent to the ideal breaker in the nominal path and a metal oxide branch in the fault circuit loop, and the DCCB main breaker remains closed due to operation time arrestor (MOA) when proactive switching control is applied [14,24]. A residential current breaker is delay [33] (Figure 16b). Thus, the fault current level and accelerating speed are limited by the FCL used to cut a residential current in the MOA, which is also modeled as an ideal breaker. The branch, which releases the overcurrent pressure on the IGBTs and diodes in the converter and reduces the requirement of the DCCB in an interruption capacity. Once the converter is blocked under an overcurrent protection, T and T are switched on to bypass L , and the DCCB main breaker is 3 4 FCL opened (Figure 16c). Consequently, R shares the fault current with the MOA in the DCCB, and the FCL fault circuit inductance is reduced to quickly extinguish the fault current. Afterward, when the current Appl. Sci. 2019, 9, x 15 of 26 Appl. Sci. 2019, 9, x 15 of 26 topologies of the DCCB and equivalent simulation model [14] are exhibited in Figure 14a and Figure topologies of the DCCB and equivalent simulation model [14] are exhibited in Figure 14a and Figure Appl. Sci. 2019, 9, 1661 15 of 26 14b, correspondingly. The main breaker demonstrated in Figure 14b will wait for the operation delay 14b, correspondingly. The main breaker demonstrated in Figure 14b will wait for the operation delay in ultrafast disconnector switch (Figure 14a) operation, and the delay time is normally 2ms [33]. The in ultrafast disconnector switch (Figure 14a) operation, and the delay time is normally 2ms [33]. The fault current with a hybrid DCCB operation is exhibited in Figure 15. level slightly decreases, the fault current will be cut via the residential current breaker. In addition, T , fault current with a hybrid DCCB operation is exhibited in Figure 15. T , T , and T are switched to their normal states. 2 3 4 MOA MOA (a) (b) (a) (b) Figure 14. (a) Direct current circuit breaker topology, (b) simplified simulation model. Figure 14. (a) Direct current circuit breaker topology, (b) simplified simulation model. Figure 14. (a) Direct current circuit breaker topology, (b) simpliﬁed simulation model. max max I Fault current B _max I Fault current without DCCB B _max without DCCB Fault current Fault current with DCCB with DCCB Fault current Fault current through arrestor through arrestor A. Fault occurs A. Fault occurs B. Fault detected B B. Fault detected C. Main breaker opens C. Main breaker opens D D. Residential current breaker opens D. Residential current breaker opens dN dN t t Bo _ p max ft t t max ft Bo _ p Appl. Sci. 2019, 9, x 16 of 26 Figure 15. Fault current with hybrid DCCB operation. Figure 15. Fault current with hybrid DCCB operation. Figure 15. Fault current with hybrid DCCB operation. D D D D 1 2 i i 1 2 fault fault Figure 16 displays the fault current interruption sequence of the EFCLC with DCCB. 𝑇 and 𝑇 Figure 16 displays the fault current interruption sequence of the EFCLC with DCCB. T T 𝑇 and 𝑇 T T 1 2 are opened during the normal state, whereas 𝑇 , 𝑇 , and the DCCB main breaker are closed. When a FCL are opened during the normal state, whereas 𝑇 , 𝑇 , and the DCCB main breaker are closed. When a R T L R T FCL 3 FCL MOA FCL 3 fault occurs, 𝑇 and 𝑇 remain open befo MOAre a fault is detected, and the main breaker of the DCCB fault occurs, 𝑇 and 𝑇 remain open before a fault is detected, and the main breaker of the DCCB remains closed (Figure 16a). Wh 4 en a fault is detected, 𝑇 and 𝑇 are switched off to insert an FCL remains closed (Figure 16a). When a fault is detected, 𝑇 and 𝑇 are switched off to insert an FCL MOA branch in the fault circui MOA t loop, and the DCCB main breaker remains closed due to operation time branch in the fault circuit loop, and the DCCB main breaker remains closed due to operation time delay [33] (Figure 16b). Thus, the fault current level and accelerating speed are limited by the FCL (a) (b) delay [33] (Figure 16b). Thus, the fault current level and accelerating speed are limited by the FCL D D branch, which releases the overcurrent pressure on the IGBTs and diodes in the converter and 1 2 D D i 1 2 fault branch, which releases the overcurrent pressure on the IGBTs and diodes in the conve fault rter and T T T 1 2 T reduces the requirement of the DCCB in an interruption capacity. O 1 nce the conve 2 rter is blocked under reduces the requirement of the DCCB in an interruption capacity. Once the converter is blocked under L L FCL FCL an overcurrent protection, 𝑇 and 𝑇 are switched on to bypass 𝐿 , and the DCCB main breaker R T R T FCL 3 FCL 3 MOA MOA an overcurrent protection, 𝑇 and 𝑇 are switched on to bypass 𝐿 , and the DCCB main breaker is opened (Figure 16c). Consequently, 𝑅 shares the fault current with the MOA in the DCCB, and T T is opened (Figure 16c). Consequently 4 , 𝑅 shares the fault current with the MOA in the DCCB, and the fault circuit inductance is reduced to quickly extinguish the fault current. Afterward, when the MOA MOA the fault circuit inductance is reduced to quickly extinguish the fault current. Afterward, when the current level slightly decreases, the fault current will be cut via the residential current breaker. In current level slightly decreases, the fault current will be cut via the residential current breaker. In (c) (d) addition,𝑇 ,𝑇 ,𝑇 , and 𝑇 are switched to their normal states. addition,𝑇 ,𝑇 ,𝑇 , and 𝑇 are switched to their normal states. Figure 16. Sequence of fault interruption. (a) After fault occurrence and before fault detection, (b) 𝑇 Figure 16. Sequence of fault interruption. (a) After fault occurrence and before fault detection, (b) T and and T𝑇 ar are swit e switched ched off o, (c , ( ) c DCCB ) DCCB operates, operates, T and 𝑇 and T ar 𝑇 e turned are turned on, ( on, (d) RCB d) RCB opens, opens, an and T and d 𝑇 T and are 2 3 4 3 4 turned 𝑇 are turned off o. . 4. Design of the Enhanced Fault Current Limiting Circuit 4.1. Design Objective The EFCLC aims to reduce the requirement for the interruption capacity and isolation speed in the DCCB. Several factors are considered to achieve the design objective. 1. The peak value of the DC line current 𝑖 must be limited under the maximum breaking current of the DCCB 𝐼 when the main breaker opens. 2. The fault current rising speed (𝑑𝑖 ⁄𝑑𝑡 ) must be lower than the largest rate of the current change withstood by the DCCB ((𝑑𝑖 𝑑𝑡 ) ). 3. In accordance with the fault current through the converter arms displayed in Figure 10, the freewheeling diodes still withstand overcurrent after blocking IGBTs. Thus, the DCCB is required to operate before the fault current reaches its maximum value. That is, the main breaker must open before the IGBT is blocked, thereby benefiting the system recovery and restart. The time period from fault occurrence to the DCCB operation (𝑡 ) must be shorter than the time consumed from fault occurrence to blocking IGBTs ( 𝑡 ). Specifically, 𝑡 involves the fault detection time (𝑡 ) and DCCB operation time (𝑡 ) (Figure 15). In accordance with the aforementioned points, the following condition can be obtained: max(iI ) < (38) dc B _max max(di / dt)(/ < di dt) (39) dc B _max tt>=t +t (40) bl op fd B _ op 4.2. Determination of Boundary Condition Reference [33] mentioned that the hybrid DCCB has been tested to interrupt the maximum fault current of 9 kA within 2 ms. Thus, 𝐼 is set to 9 kA in this study. The DCCB operation time 𝑡 _ _ is set to 2 ms. Therefore, (𝑑𝑖 𝑑𝑡 ⁄ ) is set to 9 kA/2 ms = 4.5 kA/ms. The fault detection time under the DC fault in the HVDC system has been reduced to within 1ms via a wavelet-based algorithm without using communication [40]. Consequently, the fault detection time 𝑡 can only be set to 1ms, and the capacitor discharging time 𝑡 must be more than 1 ms+2 ms =3 ms. The worst fault scenario has been adopted in this part as the PPF at the end of the DC overhead line. Furthermore, the threshold value of the arm current (𝐼 ) is normally set to twice as that of the rated current (𝐼 ) to block the IGBT. Therefore, I =2 × I = 2 × 1000A = 2000A with 𝐼 is set to 1000 A in this study. Appl. Sci. 2019, 9, 1661 16 of 26 4. Design of the Enhanced Fault Current Limiting Circuit 4.1. Design Objective The EFCLC aims to reduce the requirement for the interruption capacity and isolation speed in the DCCB. Several factors are considered to achieve the design objective. 1. The peak value of the DC line current i must be limited under the maximum breaking current dc of the DCCB I when the main breaker opens. B_max 2. The fault current rising speed (di /dt) must be lower than the largest rate of the current change dc withstood by the DCCB ((di/dt) ). B_max 3. In accordance with the fault current through the converter arms displayed in Figure 10, the freewheeling diodes still withstand overcurrent after blocking IGBTs. Thus, the DCCB is required to operate before the fault current reaches its maximum value. That is, the main breaker must open before the IGBT is blocked, thereby beneﬁting the system recovery and restart. The time period from fault occurrence to the DCCB operation (t ) must be shorter than the time consumed op from fault occurrence to blocking IGBTs (t ). Speciﬁcally, t involves the fault detection time op bl t and DCCB operation time t (Figure 15). In accordance with the aforementioned points, B_op f d the following condition can be obtained: max(i ) < I (38) dc B_max max(di /dt) < (di/dt) (39) dc B_max t > t = t + t (40) op bl f d B_op 4.2. Determination of Boundary Condition Reference [33] mentioned that the hybrid DCCB has been tested to interrupt the maximum fault current of 9 kA within 2 ms. Thus, I is set to 9 kA in this study. The DCCB operation time t is B_max B_op set to 2 ms. Therefore, (di/dt) is set to 9 kA/2 ms = 4.5 kA/ms. The fault detection time under B_max the DC fault in the HVDC system has been reduced to within 1 ms via a wavelet-based algorithm without using communication [40]. Consequently, the fault detection time t can only be set to 1ms, f d and the capacitor discharging time t must be more than 1 ms + 2 ms = 3 ms. The worst fault scenario bl has been adopted in this part as the PPF at the end of the DC overhead line. Furthermore, the threshold value of the arm current (I ) is normally set to twice as that of the rated current (I ) to block the IGBT. th Therefore, I = 2 I = 2 1000 A = 2000 A with I is set to 1000 A in this study. th N N The capacitor discharging current is deﬁned in Equation (9) on the basis of the fault current analysis discussed in Section 2. The contributions from the AC grid and distributed line capacitance are omitted here. According to Constraint (38), the time during fault detection and main breaker operation delay is 3 ms. max(i ) = i (t) < I = 9 kA (41) dc dis B_max t=3 ms The change rate in the DC fault current can be obtained using Equation (42); the change rate must be less than 4.5 kA/ms. max(di /dt) = max(i (t) ) < 4.5kA/ms (42) dc dis In reference to Equations (35) and (36), Constraint (40) must be considered to decrease the arm current at 3 ms less than the threshold value of blocking the IGBT after fault occurrence. i (t) < I = 2kA (43) arm th t=3ms Equations (35)–(37) express that the equivalent capacitance and inductance determine the fault current development and capacitor discharging time. Moreover, the fault current curve must be Appl. Sci. 2019, 9, 1661 17 of 26 separated into two stages using the proposed EFCLC (Figure 12b). Speciﬁcally, the fault current rising speed is higher in the ﬁrst 1 ms stage than in the rest time. Thus, the fault current change rate within the ﬁrst 1 ms must be limited by Constraint (42). Furthermore, the fault current value at 3 ms after fault occurrence must be obtained by superposing the fault current calculation in two discharging stages. Therefore, varying the fault circuit parameters, which are similarly considered in determining the capacitor discharging time, must be addressed. 4.3. Parametric Design Before the EFCLC is inserted in the fault circuit loop, the fault current is only limited via the smoothing reactor, which decides the maximum increase in the fault current rate. The minimum smoothing reactor can be obtained using Equation (9) considering the limitations in the DCCB withstanding fault current change rate (4.5 kA). The theoretical minimum smoothing reactor is 41.2 mH. However, the simulation result provides 43 mH with 4.2% error. The reason may be attributed to the consideration of DC line current under the normal states. The smoothing reactor L is set to 50 mH dc considering the margin. The EFCLC will be inserted to limit fault current rising speed and amplitude after detecting a fault. Thus, the fault current rising speed is less than the fault detection time; thus, Constraint (39) is satisﬁed by properly selecting a smoothing reactor. An initial test with the EFCLC has been performed. The energy dissipation resistance R is set FCL to 50 W, and the FCL reactor L is set to 100 mH. The simulation conditions “af” and “ah,” as listed FCL in Table 2, are compared here. The red dashed line in Figure 17 indicates that a fault occurs at 1.2 s and takes 1 ms to detect fault [37]. Furthermore, the delay in the IGBT of the EFCLC is disregarded here. The fault current change rate during Dt is approximately 4 kA/ms, which is expectedly limited under the maximum current change rate of the hybrid DCCB. The EFCLC is inserted in the fault current circuit at 1.201 s, and the fault current experiences a sharp decrease DI because a part of the electrical energy is stored in L . The fault current rising speed is lower during Dt than during Dt . FCL 2 1 Therefore, the fault current at 1.203 s (the main breaker opens) is limited to approximately 6.6 kA, which is far below the maximum breaking current of the DCCB. Moreover, L is bypassed by the FCL thyristor while the main breaker opens, and the fault current extinguishment can be accelerated. The initial simulation result suggests that Constraint (41) leads to the minimum value of L and R . FCL FCL Therefore, the controlled match of L and R must be investigated. The fault current at 1.201 s is FCL FCL consistently 4 kA given the unchanged fault circuit parameter. Therefore, Figure 17 presents that 4kA DI + DI < 9kA (44) 1 2 In comparison with the blue dashed-dotted line illustrated in Figure 17, two current curves share nearly the same part during Dt . Thus, DI can be obtained with a dierence between the current values 2 1 of the two discharging conditions. In accordance with Equation (9), DI is expressed as Equation (45). DI = i (t) i (t) (45) 1 dis_a f dis_ah t=1ms t=1ms Moreover, Equations (44) and (38) can be simpliﬁed as Equation (46), because the two current curves depicted in Figure 17 have nearly the same value at 1.203 s. i (t) < 9kA (46) dis_ah t=3ms The equivalent resistance R and equivalent inductance L are acquired as Equations (47) eq_ah eq_ah and (48), respectively. Thus, on the basis of Equation (9), the fault current i at 1.203 s can be dis_ah calculated. If R = 20 W, then L must be larger than 46.4 mH to limit the fault current at 1.203 s FCL FCL under 9 kA. The minimum L matched with R = 20 W has been veriﬁed via a controlled simulation FCL FCL (Figure 18). The simulation results of the EFCLC with controlled R and dierent L are compared FCL FCL (Figure 18). The fault current with the EFCLC (calculated L = 46.4 mH with R = 20 W) FCL_min FCL_min Appl. Sci. 2019, 9, x 18 of 26 values of the two discharging conditions. In accordance with Equation (9), ∆𝐼 is expressed as Equation (45). Δ=Ii ()t −i (t) (45) 1_ dis af dis_ ah tm== 11 s t ms Moreover, Equations (44) and (38) can be simplified as Equation (46), because the two current curves depicted in Figure 17 have nearly the same value at 1.203 s. it () < 9kA (46) dis _ ah tm =3 s The equivalent resistance 𝑅 and equivalent inductance 𝐿 are acquired as Equations _ _ (47) and (48), respectively. Thus, on the basis of Equation (9), the fault current 𝑖 at 1.203 s can be calculated. If 𝑅 =20 𝛺 , then 𝐿 must be larger than 46.4mH to limit the fault current at 1.203 s under 9 kA. The minimum 𝐿 matched with 𝑅 =20 𝛺 has been verified via a controlled simulation (Figure 18). The simulation results of the EFCLC with controlled 𝑅 and different 𝐿 are compared (Figure 18). The fault current with the EFCLC (calculated 𝐿 = 46.4 with 𝑅 =20 𝛺 ) reaches 9106 A at 1.203 s. Thus, the error rate of the theoretical calculation is Appl. Sci. 2019, 9, 1661 18 of 26 approximately 1.2% within a reasonable range, and the minimum 𝐿 can be set to 47mH. Constraint (43) can be analyzed using the arm current Equations (24) and (25) in Section 2. Setting reaches 9106 A at 1.203 s. Thus, the error rate of the theoretical calculation is approximately 1.2% within 𝑅 =20 𝛺 , the 𝐿 is calculated as 219mH to satisfy Constraint (43). The arm currents are a reasonable range, and the minimum L can be set to 47mH. Constraint (43) can be analyzed using compared under the calculated 𝐿 FCL and 𝐿 obtained via a simulation (Table 3). The _ _ the arm current Equations (24) and (25) in Section 2. Setting R = 20 W, the L is calculated FCL FCL_min calculated 𝐿 leads to the maximum arm current (2023.5 A), which can contribute to blocking as 219 mH to satisfy Constraint (43). The arm currents are compared under the calculated L the IGBTs. The error in the calculation method may be attributed to the circulating current FCL among _min and L obtained via a simulation (Table 3). The calculated L leads to the maximum arm FCL_min FCL_min arms. However, the simulation method provides expected results; that is, the currents of the six arms current (2023.5 A), which can contribute to blocking the IGBTs. The error in the calculation method are all limited under 2 kA at 1.203 s. Therefore, in the overall view of constrains, 𝐿 is may be attributed to the circulating current among arms. However, the simulation method provides approximately 225 mH when 𝑅 is set to 20 Ω. However, 𝐿 is selected as 250 mH with expected results; that is, the currents of the six arms are all limited under 2 kA at 1.203 s. Therefore, in 𝑅 =20 𝛺 considering the margin in the parameter setting. the overall view of constrains, L is approximately 225 mH when R is set to 20 W. However, FCL_min FCL L is selected as 250 mH with R = 20 W considering the margin in the parameter setting. FCL_min FCL RR=+ 2R +R eq _ ah fault dc FCL (47) R = R + 2R + R (47) eq_ah f ault dc FCL L =+LL 2 +L (48) eq_0 ah dc FCL L = L + 2L + L (48) eq_ah dc FCL Main breaker opens af ah EFCLC is inserted ΔI ΔI Fault occur Δt Δt 1.199 1.2 1.201 1.202 1.203 1.204 Ti Ti m m e( es /) s Appl. Sci. 2019, 9, x 19 of 26 Figure Figure 17. 17. Simulation Simulation resu results lts of of the DC the DC line line curr current with the EFCLC. ent with the EFCLC. L=43.6mH L=44mH L=45mH 9,106 L=46mH L=47mH 9,050 8,950 1.2029 1.203 1.203 1.203 -2000 1.199 1.2 1.201 1.202 1.203 1.204 Tim Time e/s (s) Figure Figure 18. 18. Simulation Simulation resu results lts of of the the contr controlle olled d R 𝑅 and and didiffere erentnt L 𝐿 . . FCL FCL Table 3. Arm currents under the calculated and simulated 𝐿 . 𝑳 = 𝟐𝟏𝟗 𝒎𝑯, 𝑹 = 𝟐𝟎 𝛀 𝑳 = 𝟐𝟐𝟓 𝒎𝑯, 𝑹 = 𝟐𝟎 𝛀 𝑳𝑭𝑪 𝑳𝑭𝑪 𝑳𝑭𝑪 𝑳𝑭𝑪 Phase-A upper arm current 1712.7 A Phase-A upper arm current 1668.3 A Phase-A lower arm current 2023.4 A Phase-A lower arm current 1999.2 A Phase-B upper arm current 2023.5 A Phase-B upper arm current 1999.1 A Phase-B lower arm current 1704.4 A Phase-B lower arm current 1680.2 A Phase-C upper arm current 1876.5 A Phase-C upper arm current 1834.3 A Phase-C lower arm current 1858.7 A Phase-C lower arm current 1852.3 A 5. Discussion Several existing FCL schemes were compared in terms of FCL ability, cost, power loss, and influence on recovery and restart operations. The energy dissipation resistance-based FCL method in Reference [14], the inductance-based FCL scheme [15,35], and the proposed EFCLC were simulated under controlled conditions in this section. 5.1. Fault Current-Limiting Ability Comparison To investigate the FCL ability, the bias voltage adopted in the scheme presented in Reference [15] is omitted for convenience, and the values of the FCL reactor and energy dissipation resistance are maintained in comparison with the FCL ability (𝑅 = 20 𝛺 , 𝐿 = 250 𝑚𝐻 ). In accordance with the FCL method in Reference [21], the AC feeding current can be limited via a parallel-connected thyristor, and the FCL ability is compared on the basis of the capacitor discharging current in the present study. Therefore, the AC feeding current is eliminated by switching off the start connector in the simulation while the DCCB operates. The simulation results of the arm and DC line currents with different FCL schemes are compared, as exhibited in Figure 19. The arm current with the resistance- based method (R-method) is limited to approximately 6 kA (Figure 19a). The arm currents with inductance-based method (I-method) and proposed scheme are restricted under 2 kA (Figure 19c and Figure 19e, respectively). The proposed method can accelerate the fault current decay while the main breaker opens. Thus, the freewheeling diodes and IGBTs can be protected from overcurrent for a long time, and the fault current isolation speed is shortened. The R-method has the worst FCL performance, thereby limiting the DC line current to approximately 18 kA (Figure 19b). By contrast, the I-method and the proposed method can restrain the DC line current under 5.5 kA (Figure 19d and Figure 19f, correspondingly). However, the DC line current with the I-method remains at a high level after the main breaker opens. In summary, the proposed scheme has an improved performance in limiting the fault current through converter arms and DC line. DC Current(A) DC current/A DC Current/A DC Current(A) 𝑚𝐻 Appl. Sci. 2019, 9, 1661 19 of 26 Table 3. Arm currents under the calculated and simulated L . FCL_min L = 219 mH, R = 20 W L = 225 mH, R = 20 W FCL FCL FCL FCL Phase-A upper arm current 1712.7 A Phase-A upper arm current 1668.3 A Phase-A lower arm current 2023.4 A Phase-A lower arm current 1999.2 A Phase-B upper arm current 2023.5 A Phase-B upper arm current 1999.1 A Phase-B lower arm current 1704.4 A Phase-B lower arm current 1680.2 A Phase-C upper arm current 1876.5 A Phase-C upper arm current 1834.3 A Phase-C lower arm current 1858.7 A Phase-C lower arm current 1852.3 A 5. Discussion Several existing FCL schemes were compared in terms of FCL ability, cost, power loss, and inﬂuence on recovery and restart operations. The energy dissipation resistance-based FCL method in Reference [14], the inductance-based FCL scheme [15,35], and the proposed EFCLC were simulated under controlled conditions in this section. 5.1. Fault Current-Limiting Ability Comparison To investigate the FCL ability, the bias voltage adopted in the scheme presented in Reference [15] is omitted for convenience, and the values of the FCL reactor and energy dissipation resistance are maintained in comparison with the FCL ability (R = 20 W, L = 250 mH). In accordance with the FCL FCL FCL method in Reference [21], the AC feeding current can be limited via a parallel-connected thyristor, and the FCL ability is compared on the basis of the capacitor discharging current in the present study. Therefore, the AC feeding current is eliminated by switching o the start connector in the simulation while the DCCB operates. The simulation results of the arm and DC line currents with dierent FCL schemes are compared, as exhibited in Figure 19. The arm current with the resistance-based method (R-method) is limited to approximately 6 kA (Figure 19a). The arm currents with inductance-based method (I-method) and proposed scheme are restricted under 2 kA (Figure 19c,e, respectively). The proposed method can accelerate the fault current decay while the main breaker opens. Thus, the freewheeling diodes and IGBTs can be protected from overcurrent for a long time, and the fault current isolation speed is shortened. The R-method has the worst FCL performance, thereby limiting the DC line current to approximately 18 kA (Figure 19b). By contrast, the I-method and the proposed method can restrain the DC line current under 5.5 kA (Figure 19d,f, correspondingly). However, the DC line current with the I-method remains at a high level after the main breaker opens. In summary, the proposed scheme has an improved performance in limiting the fault current through converter arms and DC line. 5.2. Cost The main cost of the proposed EFCLC lies in fault current-limiting inductance L , energy FCL dissipation resistance R , semiconductor switches, and surge arrester. Similar to the main breaker in FCL the hybrid DCCB, the number of IGBT depends on the voltage across the EFCLC. The amount and parameter selection of a surge arrester are also determined by protection requirement. The EFCLC can be regarded as an auxiliary circuit to share the energy absorption and electrical pressure by limiting the fault current under an acceptable level. Although IGBTs and surge arrester in EFCLC lead to extra cost, the HVDC system can ensure the fault interruption with a low risk on the DCCB failure. Moreover, according to the simulation result in Figure 19, the R-method adopted in References [14,41] has a higher fault current level than the proposed method during the fault interruption period, thereby indicating extra cost on interruption capacity, surge arrester, and the cooling system. Therefore, it might be economic to have EFCLC in protection operation, given its strength in FCL ability. Furthermore, lower peak fault current indicates less investment in DCCB interruption capability. The main expenditure of the I-method depends on the SFCL inductance technology because its unique characteristics can limit the fault current without aecting the system’s dynamic response speed. However, the immaturity of Appl. Sci. 2019, 9, 1661 20 of 26 the SFCL device leads to an increased cost to satisfy the protection requirement in terms of the system recovery and restart. Furthermore, compared with the proposed approach, the I-method requires additional cost in the energy dissipation component to accelerate the fault current extinguishment. In summary Appl. Sci. 2019 , taking , 9, x comprehensive consideration of economic eciency and FCL performance, EFCLC 20 of 26 deserves consideration to be applied in real project. 7000 20000 -1000 -5000 1.18 1.2 1.22 1.24 1.26 1.28 1.18 1.2 1.22 1.24 1.26 1.28 Time(s) Time(s) (a) (b) 2000 6000 -500 -1000 1.18 1.2 1.22 1.24 1.26 1.28 1.18 1.2 1.22 1.24 1.26 1.28 Time(s) Time(s) (c) (d) 2000 6000 -500 -1000 1.18 1.2 1.22 1.24 1.26 1.28 1.18 1.2 1.22 1.24 1.26 1.28 Time(s) Time(s) (e) (f) Figure 19. FCL ability comparison among existing methods: (a) Arm current in the resistance-based Figure 19. FCL ability comparison among existing methods: (a) Arm current in the resistance-based method, (b) DC line current in the resistance-based, (c) Arm current in the inductance-based method, method, (b) DC line current in the resistance-based, (c) Arm current in the inductance-based method, (d) DC line current in the inductance-based method, (e) Arm current in the proposed method, (f) DC (d) DC line current in the inductance-based method, (e) Arm current in the proposed method, (f) DC line current in the proposed method. line current in the proposed method. 5.3. Power Loss 5.2. Cost As explained in Section 4.3, the proposed scheme requires a smoothing reactor of 50 mH, thereby The main cost of the proposed EFCLC lies in fault current-limiting inductance 𝐿 , energy leading to power loss during the normal state. Considering that the resistance value of a 2 mH reactor dissipation resistance 𝑅 , semiconductor switches, and surge arrester. Similar to the main breaker equals 18.9 mW [42], the power loss P is expressed as Equation (49). in the hybrid DCCB, the number of IGBT depends on the voltage across the EFCLC. The amount and parameter selection of a surge arrester are also determined by protection requirement. The EFCLC 4I R L L r dN can be regarded as an auxiliary circuit to share the energy absorption and electrical pressure by P = 100% (49) cableN limiting the fault current under an acceptable level. Although IGBTs and surge arrester in EFCLC lead to extra cost, the HVDC system can ensure the fault interruption with a low risk on the DCCB failure. Moreover, according to the simulation result in Figure 19, the R-method adopted in References [14,41] has a higher fault current level than the proposed method during the fault interruption period, thereby indicating extra cost on interruption capacity, surge arrester, and the cooling system. Therefore, it might be economic to have EFCLC in protection operation, given its strength in FCL ability. Furthermore, lower peak fault current indicates less investment in DCCB Arm current(A) Arm current(A) Arm current(A) DC line current(A) DC line current(A) DC line current(A) Appl. Sci. 2019, 9, x 21 of 26 interruption capability. The main expenditure of the I-method depends on the SFCL inductance technology because its unique characteristics can limit the fault current without affecting the system’s dynamic response speed. However, the immaturity of the SFCL device leads to an increased cost to satisfy the protection requirement in terms of the system recovery and restart. Furthermore, compared with the proposed approach, the I-method requires additional cost in the energy dissipation component to accelerate the fault current extinguishment. In summary, taking comprehensive consideration of economic efficiency and FCL performance, EFCLC deserves consideration to be applied in real project. 5.3. Power Loss As explained in Section 4.3, the proposed scheme requires a smoothing reactor of 50 mH, thereby leading to power loss during the normal state. Considering that the resistance value of a 2 mH reactor equals 18.9 mΩ [42], the power loss 𝑃 is expressed as Equation (49). 4IR L dN L r P=×100% (49) Appl. Sci. 2019, 9, 1661 21 of 26 cableN where 𝐼 is the rated DC line current, 𝑅 = 0.00945 Ω/mH is based on Reference [43], 𝐿 is the where I is the rated DC line current, R = 0.00945 W/mH is based on Reference [43], L is the dN L r smoothing reactor, and 𝑃 is the rated DC line power. Thus, the smoothing reactor in the smoothing reactor, and P is the rated DC line power. Thus, the smoothing reactor in the proposed cablrN proposed scheme causes 0.135% power loss in comparison with the rated DC line power, thus scheme causes 0.135% power loss in comparison with the rated DC line power, thus denoting a denoting a promising economic efficiency. promising economic eciency. 5.4. Influence on Fault Current 5.4. Inﬂuence on Fault Current Figure 20a,b presents the influence of 𝑅 and 𝐿 on the DC line current, respectively. When Figure 20a,b presents the inﬂuence of R and L on the DC line current, respectively. When FCL FCL 𝑅 increases but 𝐿 remains at 250 mH, the DCCB capability requirement is low, and the fault R increases but L remains at 250 mH, the DCCB capability requirement is low, and the fault FCL FCL current extinguishment is accelerated (Figure 20a). When 𝐿 increases but 𝑅 remains at 20 Ω, current extinguishment is accelerated (Figure 20a). When L increases but R remains at 20 W, FCL FCL the peak value of the fault current decreases but the time spent in the fault current interruption is the peak value of the fault current decreases but the time spent in the fault current interruption is unaffected. Therefore, 𝐿 in the proposed scheme hardly influences the dynamic response or the unaected. Therefore, L in the proposed scheme hardly inﬂuences the dynamic response or the FCL fault current extinguishment. fault current extinguishment. 12000 12000 without EFCLC without EFCLC L =200mH FCL R =10Ω FCL L =300mH FCL R =20Ω FCL 8000 8000 L =400mH FCL R =50Ω FCL L =500mH FCL 6000 6000 R =100Ω FCL 4000 4000 2000 2000 0 0 1.2 1.205 1.21 1.215 1.22 1.225 1.23 1.235 1.2 1.205 1.21 1.215 1.22 1.225 1.23 1.235 Time(s) Time(s) (a) (b) Figure 20. DC line current with variables (a) 𝑅 and (b) 𝐿 . Figure 20. DC line current with variables (a) R and (b) L . FCL FCL 5.5. Inﬂuence on Energy Absorption 5.5. Influence on Energy Absorption Because of the isolation eect of the thyristor on the AC feeding current, the fault current during fault interruption is mainly the freewheeling current, given the energy stored in the smoothing reactor, whose path is depicted in Figure 21. The energy stored in the smoothing reactor can be obtained using Equation (50). E = 1/2L i (t ) (50) L dc op f ault where L is the smoothing reactor; i t is the fault current through the DC line while the DCCB dc f ault op operates, which can be obtained using Equation (9); and t is the time point of fault occurrences. t t op 0 C eq I ! dis0 0 i (t ) = e [U sin(! (t t )) sin(! (t t ) )] (51) op op op f ault dc 1 0 1 0 L ! eq 1 Appl. Sci. 2019, 9, x 22 of 26 D D 1 2 dc fault T T + 1 2 M − RCB FCL FCL 3 MOA + + − U − C 4 MOA Figure 21. Fault current path during fault interruption. Figure 21. Fault current path during fault interruption. Because of the isolation effect of the thyristor on the AC feeding current, the fault current during fault interruption is mainly the freewheeling current, given the energy stored in the smoothing reactor, whose path is depicted in Figure 21. The energy stored in the smoothing reactor can be obtained using Equation (50). E = 1/ 2Li (t ) (50) L dc fault op where 𝐿 is the smoothing reactor; 𝑖 (𝑡 ) is the fault current through the DC line while the DCCB operates, which can be obtained using Equation (9); and 𝑡 is the time point of fault occurrences. tt − op 0 − C I ω eq dis00 it ( )=− e [U sin(ωω (t t ))− sin( (t−t )−θ )] (51) fault op dc 10 op 1 op 0 L ω eq 1 The energy absorbed by 𝑅 can be expressed as EU== (/R )dtR(( i ) /R )dt (52) R R FCL FCL fault FCL  Then, the energy absorbed in the MOA of the DCCB can be expressed as E =−EE (53) M LR Figure 20b displays that a large smoothing reactor will lead to a small 𝑖 (𝑡 ). Thus, the energy stored in the smoothing reactor will decrease, thereby indicating a reduced energy consumed in the MOA and decreased time spent in the fault current interruption. Moreover, the fault detection time can influence the energy stored in the smoothing reactor in a positive relationship. Thus, determining the energy absorbed in 𝑅 must consider the effect of inductance and fault detection time to reduce stress on the MOA of the DCCB. The simulation result presented in Figure 22a shows that a large 𝑅 results in minimal energy absorption in the MOA of the DCCB given the low fault current level at the DCCB operation time point and shared energy absorption. Similarly, a large 𝐿 denotes a minimal energy absorbed in the MOA because an increase in 𝐿 leads to a low current and energy stored in 𝐿 when the main breaker opens. Overall, 𝑅 and 𝐿 can limit the fault current to a relatively low level to reduce the energy absorbed in the MOA of the DCCB. However, a balance between the DCCB and EFCLC is observed in terms of energy consumption during the fault current-limiting period and fault current extinguishment stage. Therefore, the tradeoff between FCL performance and additional cost on the snubber circuit and cooling system of the EFCLC must be considered. DC line current(A) DC line current(A) Appl. Sci. 2019, 9, 1661 22 of 26 The energy absorbed by R can be expressed as FCL Z Z E = (U /R )dt = ((R i ) /R )dt (52) FCL FCL f ault FCL Then, the energy absorbed in the MOA of the DCCB can be expressed as E = E E (53) M L R Figure 20b displays that a large smoothing reactor will lead to a small i t . Thus, the energy op f ault stored in the smoothing reactor will decrease, thereby indicating a reduced energy consumed in the MOA and decreased time spent in the fault current interruption. Moreover, the fault detection time can inﬂuence the energy stored in the smoothing reactor in a positive relationship. Thus, determining the energy absorbed in R must consider the eect of inductance and fault detection time to reduce FCL stress on the MOA of the DCCB. The simulation result presented in Figure 22a shows that a large R FCL results in minimal energy absorption in the MOA of the DCCB given the low fault current level at the DCCB operation time point and shared energy absorption. Similarly, a large L denotes a minimal FCL energy absorbed in the MOA because an increase in L leads to a low current and energy stored in FCL L when the main breaker opens. Overall, R and L can limit the fault current to a relatively low dc FCL FCL level to reduce the energy absorbed in the MOA of the DCCB. However, a balance between the DCCB and EFCLC is observed in terms of energy consumption during the fault current-limiting period and fault Appl. curr Sci. ent 2019extinguishment , 9, x stage. Therefore, the tradeo between FCL performance and additional 23 of 26 cost on the snubber circuit and cooling system of the EFCLC must be considered. x 10 4.5 L =500mH L =200mH FCL FCL 3.5 L =400mH L =300mH FCL FCL L =300mH L =400mH FCL FCL 2.5 L =200mH L =500mH FCL FCL 1.5 0.5 20 40 60 80 100 20 40 60 80 100 R (Ω) R (Ω) FCL FCL (a) (b) Figure 22. Characteristic curves of absorbed energy and interruption time under variables (a) 𝑅 Figure 22. Characteristic curves of absorbed energy and interruption time under variables (a) R and FCL and (b) 𝐿 . (b) L . FCL 5.6. Inﬂuence on Fault Interruption Time 5.6. Influence on Fault Interruption Time Although L is involved in the EFCLC, it can still be bypassed by the thyristor after the main FCL Although 𝐿 is involved in the EFCLC, it can still be bypassed by the thyristor after the main breaker operates. Thus, the fault current extinguishment speed cannot be delayed due to large breaker operates. Thus, the fault current extinguishment speed cannot be delayed due to large inductance. As mentioned in Section 5.5, the fault current level is restricted by a large R and FCL inductance. As mentioned in Section 5.5, the fault current level is restricted by a large 𝑅 and 𝐿 , L , and the interruption time can be reduced at a low fault current level at the beginning of fault FCL and the interruption time can be reduced at a low fault current level at the beginning of fault extinguishment. According to the expression of the attenuation coecient during the fault interruption extinguishment. According to the expression of the attenuation coefficient during the fault expressed in Equation (37), the large R can accelerate extinguishment speed. In summary, the FCL interruption expressed in Equation (37), the large 𝑅 can accelerate extinguishment speed. In interruption time is reduced when the values of R and L are high. This result agrees with the FCL FCL summary, the interruption time is reduced when the values of 𝑅 and 𝐿 are high. This result simulation result demonstrated in Figure 22b. agrees with the simulation result demonstrated in Figure 22b. 5.7. Practicality and Necessity of Proposed Circuit According to the study in this section, the proposed FCL circuit has better performance in limiting fault current under DC pole-to-pole fault, compared with previous FCL method under same parameter setting. In the viewpoint of reality, the power loss during normal state is considered acceptable as analyzed in section 5.3. In order to cooperate with protection relaying, the proposed FCL circuit is installed at the ends of transmission line so that communication delay among DCCB, measure point and protection relay could be reduced. Moreover, big smoothing reactor (200 mH) in [42–44] would influence the dynamic response speed and proposed FCL circuit could help reduce value of smoothing reactor for better performance of dynamic response. However, it requires further investigation on economic efficiency of proposed method, considering previous FCL methods, such as superconductor based fault current limiter, FCL circuit and converter topology based approach. Another point should be noted that the proposed EFCLC would make more contribution to fault interruption and clearance, compared with traditional FCL behavior with DC terminal reactor. The basic advantage of EFCLC over DC terminal reactor could be summarized as following aspects. Firstly, EFCLC is only triggered as fault detected to limit fault current, thereby having no influence on normal state and system dynamic response. By contrast, to achieve the same level of FCL performance of EFCLC, larger DC terminal reactor is required even under normal state, which does affect system dynamic response. Seconded, compared with DC terminal reactor, EFCLC could accelerate fault clearing speed due to its energy dissipation resistor. The last but not the least, the FCL inductor in EFCLC would be bypassed after IGBT blocks. Hence, the fault isolation time would be reduced to some degree since remained inductor would delay the fault current clearance. 5.8. Effectiveness of the Proposed Circuit E (J) t (ms) IN Appl. Sci. 2019, 9, 1661 23 of 26 5.7. Practicality and Necessity of Proposed Circuit According to the study in this section, the proposed FCL circuit has better performance in limiting fault current under DC pole-to-pole fault, compared with previous FCL method under same parameter setting. In the viewpoint of reality, the power loss during normal state is considered acceptable as analyzed in Section 5.3. In order to cooperate with protection relaying, the proposed FCL circuit is installed at the ends of transmission line so that communication delay among DCCB, measure point and protection relay could be reduced. Moreover, big smoothing reactor (200 mH) in [42–44] would inﬂuence the dynamic response speed and proposed FCL circuit could help reduce value of smoothing reactor for better performance of dynamic response. However, it requires further investigation on economic eciency of proposed method, considering previous FCL methods, such as superconductor based fault current limiter, FCL circuit and converter topology based approach. Another point should be noted that the proposed EFCLC would make more contribution to fault interruption and clearance, compared with traditional FCL behavior with DC terminal reactor. The basic advantage of EFCLC over DC terminal reactor could be summarized as following aspects. Firstly, EFCLC is only triggered as fault detected to limit fault current, thereby having no inﬂuence on normal state and system dynamic response. By contrast, to achieve the same level of FCL performance of EFCLC, larger DC terminal reactor is required even under normal state, which does aect system dynamic response. Seconded, compared with DC terminal reactor, EFCLC could accelerate fault clearing speed due to its energy dissipation resistor. The last but not the least, the FCL inductor in EFCLC would be bypassed after IGBT blocks. Hence, the fault isolation time would be reduced to some degree since remained inductor would delay the fault current clearance. 5.8. Eectiveness of the Proposed Circuit With application of the proposed EFCLC in fault loop, the requirement of DCCB’s interruption ability is reduced, and fault current interruption speed is accelerated. A comparison is performed in Table 4 between a fault situation with EFCLC and that without EFCLC, in terms of maximum fault current and fault interruption time. As mentioned in Section 4.3, L and R are set as 250 mH FCL_min FCL and 20 W in the test circuit. The test results shown in Table 3 reﬂect that the peak fault current needed to interrupt at DCCB operation is reduced from 12.4 kA to 5.1 kA with the help of EFCLC. Meanwhile, the time taken for the whole fault interruption process decreases from 34.8 ms to 13.6 ms. In summary, the eectiveness of the proposed circuit is veriﬁed, and reduced peak fault current and accelerated fault interruption would contribute to lower cost in relay and fast fault clearance. Table 4. Eectiveness veriﬁcation of enhance fault current limiting circuit. Term Requirement of Fault Current Interruption Fault Interruption Time Without EFCLC 12.4 kA 34.8 ms With EFCLC 5.1 kA 13.6 ms Improvement 41.1% 39.1% 6. Conclusions An EFCLC has been proposed and investigated in this study to reduce the DCCB requirement in terms of fault interruption capability and breaking speed. The EFCLC mainly consists of the energy dissipation resistor and FCL reactor. These devices are plugged into the fault loop after fault detection to limit the fault current rising speed and fault current level. Thus, while the DCCB operates, the fault current level is restrained, and the energy stored in the smoothing reactor is also reduced. Consequently, the fault current extinguishment stage can be accelerated given the increased energy dissipation resistor and decreased energy storage. Furthermore, the FCL reactor can be bypassed to accelerate the decaying of the freewheeling current. Moreover, the AC feeding current is eliminated via the bidirectional parallel-connected thyristor, whose feasibility and eectiveness have been veriﬁed in Appl. Sci. 2019, 9, 1661 24 of 26 existing works. Thus, this study focused on the methods for limiting fault current caused by capacitor discharging in the FCLC design. The proposed EFCLC has been veriﬁed to limit fault current under an expected level with a proper parameter setting on components. However, the performance tradeo and additional cost of the EFCLC must be considered in terms of the cooling system, surge arrester, and overvoltage protection. The development of the EFCLC in the multi-terminal HVDC system, the related fault protection scheme, and the FRT strategy will be investigated in future research. Author Contributions: All the authors have contributed to this paper in dierent aspects. Q.H. proposed the original concept and wrote the original draft. K.L. and L.Q. acted as supervisor and gave suggestions on paper improvement. S.Z., X.L. and Y.L. helped with software simulation and methodology improvement. Last but not least, H.D. contributed to paper editing and reviewing. Funding: This work was supported in part by the National Key Research and Development Project (Grant No. 2018YFB0904600). Conﬂicts of Interest: The authors declare no conﬂict of interest. References 1. Deng, F.; Tian, Y.; Zhu, R.; Chen, Z. Fault-tolerant approach for modular multilevel converters under submodule faults. IEEE Trans. Ind. Electron. 2016, 63, 7253–7263. [CrossRef] 2. Cui, S.; Sul, S.K. A comprehensive DC short-circuit fault ride through strategy of hybrid modular multilevel converters (MMCs) for overhead line transmission. IEEE Trans. Power Electron. 2016, 31, 7780–7796. [CrossRef] 3. Farhadi, M.; Mohammed, O.A. Protection of multi-terminal and distributed DC systems: Design challenges and techniques. Electr. Power Syst. Res. 2017, 143, 715–727. [CrossRef] 4. Yang, J.; Fletcher, J.E.; O’Reilly, J. Short-circuit fault and grounded fault analyses and location in VSC-based DC network cables. IEEE Trans. Ind. Electron. 2012, 59, 3827–3837. [CrossRef] 5. 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Publisher: Multidisciplinary Digital Publishing Institute
Copyright: © 1996-2019 MDPI (Basel, Switzerland) unless otherwise stated
ISSN: 2076-3417
DOI: 10.3390/app9081661
Publisher site: See Article on Publisher Site

Abstract

applied sciences Article Enhanced Fault Current-Limiting Circuit Design for a DC Fault in a Modular Multilevel Converter-Based High-Voltage Direct Current System 1 1 , 1 , 1 1 1 Kaipei Liu , Qing Huai * , Liang Qin * , Shu Zhu , Xiaobing Liao , Yuye Li and Hua Ding School of Electrical Engineering and Automation, Wuhan University, Wuhan 430072, China; kpliu@whu.edu.cn (K.L.); whuzhushu@163.com (S.Z.); xbliao@whu.edu.cn (X.L.); liyuye@whu.edu.cn (Y.L.) State Grid Energy Conservation Service Co., Ltd., Beijing 100052, China; huaworking@163.com * Correspondence: qinghuai315@whu.edu.cn (Q.H.); qinliang@whu.edu.cn (L.Q.); Tel.: +86-1347-683-0019 (Q.H.); +86-1898-617-2977 (L.Q.) Received: 20 March 2019; Accepted: 18 April 2019; Published: 22 April 2019 Abstract: The main weakness of the half-bridge modular multilevel converter-based high-voltage direct current (MMC-HVDC) system lies in its immature solution to extremely high current under direct current (DC) line fault. The development of the direct current circuit breaker (DCCB) remains constrained in terms of interruption capacity and operation speed. Therefore, it is essential to limit fault current in the MMC-HVDC system. An enhanced fault current-limiting circuit (EFCLC) is proposed on the basis of fault current study to restrict fault current under DC pole-to-pole fault. Speciﬁcally, the EFCLC consists of fault current-limiting inductance L and energy dissipation FCL resistance R in parallel with surge arrestor. L reduces the fault current rising speed, together FCL FCL with arm inductance and smoothing reactor. However, in contrast to arm inductance and smoothing reactor, L will be bypassed via parallel-connected thyristors after blocking converter to prevent FCL the eect on fault interruption speed. R shares the stress on energy absorption device (metal FCL oxide arrester) to facilitate fault interruption. The DCCB requirement in interruption capacity and breaking speed can be satisﬁed eortlessly through the EFCLC. The working principle and parameter determination of the EFCLC are presented in detail, and its eectiveness is veriﬁed by simulation in RT-LAB and MATLAB software platforms. Keywords: fault current-limiting circuit; DC circuit breaker; MMC-HVDC; fault protection 1. Introduction Fault vulnerability and protection immaturity constrain the development of the voltage source converter-based high-voltage direct current (VSC-HVDC) system, especially in terms of DC side fault at high power levels. Thus, reliability has become an important challenge in multilevel converter-based (MMC)-HVDC with long-distance transmission lines [1,2]. The lack of a perfect fault isolation scheme and mature DC switchgear products are the primary issues [3]. However, the VSC-HVDC system has attracted worldwide attention and research interests due to its advantages with respect to control ﬂexibility and interconnection feasibility. A related analysis of DC faults has been performed to enhance its fault ride through (FRT) ability under DC fault in the VSC-HVDC system [4,5]. An overview of HVDC system protection mentions that the major limitation in development of VSC-HVDC is the inability to limit fault current, given the limitation of the DC circuit breaker (DCCB) in interruption capability and operation speed [6]. Moreover, limiting fault current can protect the semiconductor device from excessive electrical pressure, particularly insulated gate bipolar thyristor (IGBT) and Appl. Sci. 2019, 9, 1661; doi:10.3390/app9081661 www.mdpi.com/journal/applsci Appl. Sci. 2019, 9, 1661 2 of 26 freewheeling diode in a converter sub-module (SM). Furthermore, restriction of fault current can provide additional time for fault detection and operation delay. Therefore, limiting fault current development and propagation in the VSC-HVDC and multi-terminal HVDC (MTDC) systems is essential. State-of-the-art fault current-limiting (FCL) techniques can be classiﬁed into improved SM topologies [7–12], auxiliary FCL circuits (FCLC) [13–20], and fault current limiters [21–25]. The SM topology has been modiﬁed to reinforce its fault handling ability, because the classical half-bridge SM (HBSM) is likely to be destroyed under overcurrent if no proper protection scheme is applied, even if insulated gate bipolar translators (IGBTs)are blocked in a timely fashion [26]. Thus, several innovative improvements, including full-bridge SM (FBSM) [7,8], clamp double SM (CDSM) [9], and hybrid SM, which combines FBSM and HBSM, have been conceived in the SM topology design [10]. Although the FBSM solution can ride through faults without blocking the converter, given its ability to output bipolar voltage, regardless of arm current direction [9], the doubled number and on-state loss of semiconductors are their main drawbacks. A CDSM solution only has 50% higher semiconduction than the HBSM to extinguish the DC arc by blocking IGBTs under nonpermanent fault [10]. However, the MMC converter has generally been regarded as the most appropriate static synchronous compensator to support alternating current (AC) grids in DC pole-to-pole fault scenarios [11]. Thus, enhancing the FRT capability without blocking the converter is crucial. A hybrid MMC topology requires each arm to have the same amount of FBSM and HBSM by considering their nature [10,12]. Thus, the cost of semiconductor devices and conduction losses have been reduced in comparison with those in the FBSM. However, further research on control strategies in terms of dynamic characteristics and SM voltage balancing is required [2]. Overall, control complexity and high cost are the weaknesses of SM topology-based solutions. Another FCL technology relies on an auxiliary circuit, which consistently includes energy dissipation resistance and an FCL reactor. For example, a hybrid current-limiting circuit (Figure 1a) has been designed to restrain the DC line fault current in the MTDC system [13], which is settled at the end of the DC line between the DCCB and DC converter ports. The energy dissipation resistance R is equipped to share the stress on energy absorption element in the DCCB, and the fault current interruption speed is accelerated. However, the tradeo between FCL performance and the extra cost of the resistor must be considered. In addition, a bridge-type FCLC is composed of a DC voltage source, a DC reactor, and four groups of diodes (Figure 1b) [14]. Reference [14] shows that the DC biased current given by the DC power supply is considered to be the threshold value of the DC fault current in order to automatically activate the FCLC itself. The main advantage is that the DC reactor can be bypassed in its normal state and after turning o the main breaker of the DCCB. In addition, the idea of the FCLC is also reﬂected in the form of an SM [15], which is inserted into each arm in series. However, the FCL-SM can only limit a unidirectional fault current, and the surge voltage across FCL-SM must be given further attention. Moreover, an enhanced reverse blocking SM (ERBSM) topology has been proposed to extinguish a fault current arc by inverse voltage [16]. Control complexity is reduced because the ERBSM adopts the same modulation strategy. In Reference [17], thyristors have better performance than diode in withstanding overcurrent (Figure 1e), and the overcurrent pressure on freewheeling diode has been relieved via the shunting eect of a single-thyristor switch scheme (STSS) [17–19]. Although the STSS can protect semiconductor devices, the AC grid current fed into the DC side cannot be prevented. Thus, the double-thyristor switch scheme (DTSS) has been introduced to protect the DC overhead line (Figure 1f), which can eliminate the freewheeling eect of diodes, and the DC line fault current can freely decay to zero [20]. Then, the DC fault is transformed into an AC short circuit fault that can be cleared by switching o the thyristor. However, the high dv/dt across thyritors and the sharing current eect of bypassed diodes are ignored in the DTSS solution. To solve this problem, double-thyristor switches are combined and connected at the AC port of the converter instead of across the diode in the SM to isolate the AC side from the DC side when a fault occurs. Moreover, the feasibility of such a scheme has been veriﬁed via a case study that considers STSS and DTSS in a classical VSC-HVDC system, as well as MMC-HVDC. Appl. Sci. 2019, 9, 1661 3 of 26 The superconducting fault limiter (SFCL) has attracted considerable attention because its nonlinear impedance characteristics can be used to limit the increase in fault current rate to provide a necessary time for relay protection. The SFCL can mainly be divided into resistive-SFCL (R-SFCL) and inductive-SFCL (I-SFCL) [21]. The study concludes that R-SFCL can constrain the amplitude of fault current, but reduces the increase in fault current rate dierently, and I-SFCL can delay the increase in fault rate signiﬁcantly [22]. Related research has been performed on the basis of the unique characteristics in SFCL. For example, R-SFCL has been thoroughly investigated on the basis of the current-limiting capability comparison and parameter inﬂuence, thus indicating that the use of R-SFCL is suggested for real applications, provided that it is suciently sensitive to develop an adequate quenching resistance [23]. Hybrid DCCB has been equipped with SFCL in the main line to limit the fault current until a fault is completely interrupted [24,25]. In addition, the superconducting magnetic energy storage technique has been adopted to limit fault current, which is achieved via a power transform between the power system and superconducting coil [26]. A rapid limitation can be realized when controlled FCL (molded as pancakes) is isolated to maintain its dynamic stability. In contrast to the AC line fault current, the fault current under DC short circuit fault in the MMC-HVDC system does not have a natural zero crossing. Thus, applying DCCB has been limited given its high cost and technical immaturity [27]. Mechanical breakers can limit fault current in a few tens of milliseconds but cannot satisfy the demand in the VSC-HVDC system protection [28]. Although semiconductor circuit breakers have a large on-state loss, the operation speed requirement is satisﬁed. The hybrid HVDC breaker has been proposed and investigated in References [29–31] to eliminate on-state power loss and limit fault current within several milliseconds. Parametric analysis of hybrid DCCB has also been conducted thoroughly considering the inﬂuence of the main parameters on the system and the breaker design [32]. Moreover, an interlink DCCB has been proposed to maintain the fault current interruption ability with a few components to reduce the overall cost of the DCCB in the DC grid [33]. In Reference [24], varying the DC current is considered an underdamping decay process, given the small resistance in the fault circuit. Thus, the fault current-limiting inductance L cannot change FCL the damping characteristics which refer to criterion R < 2 L/C. That is, L can only limit DC fault FCL current, but not relieve the overcurrent eect in the converter and AC sides [24]. The SFCL has not been applied extensively in real projects because of its high cost and lack of maturity, particularly with respect to SFCL recovery after being activated. The main advantage of the SFCL is that it does not inﬂuence the dynamic response under normal state. The direct installation of the DC reactor aects the system’s normal operation and DCCB isolation speed [34]. Therefore, the present study proposes an enhanced fault current-limiting circuit (EFCLC) that primarily consists of energy dissipation resistance, limiting reactor, surge arrester, and semiconductor switches on the basis of existing works. The EFCLC aims to limit fault current through converter arms and DC line before the DCCB operates, thereby decreasing the peak current for fault interruption and reducing overcurrent eect on converter arms. Moreover, the required DCCB capability could be reduced, given limited fault current with EFCLC and more time is saved for fault detection, since fault current rising speed is more or less restricted. The remainder of this paper is organized as follows. Section 2 thoroughly analyzes DC fault current on the basis of theoretical calculation and simulation veriﬁcation. Section 3 presents the topology and working principle of EFCLC. Section 4 performs the parametric design study of EFCLC. Section 5 further investigates the proposed scheme with EFCLC in terms of FCL ability and cost. Finally, Section 6 summarizes the conclusion and future scope. 2. DC Fault Current Analysis 2.1. Test System Introduction The scheme of the MMC-HVDC system can be categorized into monopolar and bipolar symmetrical wiring systems (Figure 1). The monopolar symmetrical HVDC system is also known as the pseudo Appl. Sci. 2019, 9, 1661 4 of 26 Appl. Sci. 2019, 9, x 4 of 26 bipolar HVDC system, which typically adopts a cable as a DC line. However, a real bipolar HVDC system is commonly applied in the HVDC transmission system with a high-capacity and overhead DC bipolar HVDC system is commonly applied in the HVDC transmission system with a high-capacity line. The main dierence between the two schemes lies in operation mode. Bipolar systems can work and overhead DC line. The main difference between the two schemes lies in operation mode. Bipolar under both monopolar mode and bipolar mode. Namely, the power transmission of the positive pole systems can work under both monopolar mode and bipolar mode. Namely, the power transmission overhead line and negative pole overhead line is independent. Therefore, bipolar systems can work of the positive pole overhead line and negative pole overhead line is independent. Therefore, bipolar during fault by transferring power through healthy line (monopolar mode). In contrast, monopolar systems can work during fault by transferring power through healthy line (monopolar mode). In systems cannot maintain power transmission under fault, since they only operate under monopolar contrast, monopolar systems cannot maintain power transmission under fault, since they only mode. Hence, the bipolar system demonstrates advantages in terms of power supply reliability and operate under monopolar mode. Hence, the bipolar system demonstrates advantages in terms of FRT capability. power supply reliability and FRT capability. Positive pole cable MMC Negative pole cable MMC (a) Positive pole overhead line MMC MMC Metallic return MMC MMC Negative pole overhead line (b) Figure 1. Diagram of the modular multilevel converter-based high-voltage direct current system in Figure 1. Diagram of the modular multilevel converter-based high-voltage direct current system in (a) (a) monopolar symmetrical wiring and (b) bipolar symmetrical wiring. monopolar symmetrical wiring and (b) bipolar symmetrical wiring. The MMC-HVDC system mainly consists of modular multilevel converter stations and DC line The MMC-HVDC system mainly consists of modular multilevel converter stations and DC line part parts. s. The t The topology opology st str ructur ucture of e of MMC, MMC, which which inc includes ludesthr thee ree convert converter er unit units,sis , is displayed displayed in in Figur Figu ere 2. Each unit involves upper and lower bridge arms that are connected with the bridge arm reactor L . 2. Each unit involves upper and lower bridge arms that are connected with the bridge arm reactor 𝐿 . The SMs ar The SMs aree connected connected in in series serie in s every in ever bridge y bridge arm, arm which , wh consists ich conof sists o twofswitches, two switches, name namely, T and ly, T 𝑇 1 2 (IGBT); anti-parallel connected diodes, namely, D and D ; and energy storage capacitor C . The DC and 𝑇 (IGBT); anti-parallel connected diodes, namely, 𝐷 and 𝐷 ; and energy storage capacitor 𝐶 . 1 2 0 The DC volt voltage is maintained age is maby inta switch ined by sw ing T it and ching T 𝑇on and and o 𝑇 in onevery and o SM ff in tripped every S by Ma tcontr ripped by ol signal. a cont If the rol 1 2 amount of SMs in each converter unit is 2N, then it has N switched-on and N switched-o SMs during signal. If the amount of SMs in each converter unit is 2N, then it has N switched-on and N switched- off SMs during normal operation. normal The DC operat sideion. voltage The U DC side vo is equalltto agthe e 𝑈 sum is e of q the uaswitched-on l to the sum of SMth voltage e switched- U . The on DC 0 main modulation modes are divided into pulse width modulation and nearest level modulation. The SM voltage 𝑈 . The main modulation modes are divided into pulse width modulation and nearest level converter modu stations lation. The conv are blocked erte by r st turning ations are o block IGBTs ed in by t all u SMs rning given off IG the BTs in local al over l SM curr s given ent pr tote he ction local when a current reaches a threshold value (normally twice the value of the nominal current). overcurrent protection when a current reaches a threshold value (normally twice the value of the nominal current). Appl. Sci. 2019, 9, 1661 5 of 26 Appl. Sci. 2019, 9, x 5 of 26 Figure 2. Topology structure of the MMC. Figure 2. Topology structure of the MMC. 2.2. DC Fault Analysis of the Test System 2.2. DC Fault Analysis of the Test System In the monopolar MMC-HVDC system, the DC line is typically composed of cables because the In the monopolar MMC-HVDC system, the DC line is typically composed of cables because the fault possibility is considered much lower in cables than in overhead lines [35]. However, an overhead fault possibility is considered much lower in cables than in overhead lines [35]. However, an line is typically adopted in the bipolar system, especially in long-distance power transmission with a overhead line is typically adopted in the bipolar system, especially in long-distance power high capacity. Given that an overhead line is likely to be aected by a short circuit, grounded fault, and transmission with a high capacity. Given that an overhead line is likely to be affected by a short nonpermanent fault, analyzing the fault characteristics for protection relaying is necessary. The DC circuit, grounded fault, and nonpermanent fault, analyzing the fault characteristics for protection line faults are mainly classiﬁed into a single pole-to-ground fault, pole-to-pole short-circuit fault (PPF), relaying is necessary. The DC line faults are mainly classified into a single pole-to-ground fault, pole- and line disconnection. The PPF is regarded as a serious fault considering an extremely high fault to-pole short-circuit fault (PPF), and line disconnection. The PPF is regarded as a serious fault current within a few milliseconds after fault occurrence. In Figure 2, the MMC-HVDC scheme indicates considering an extremely high fault current within a few milliseconds after fault occurrence. In Figure that the single pole-to-ground fault in the bipolar system can be equivalent to the PPF given bipolar 2, the MMC-HVDC scheme indicates that the single pole-to-ground fault in the bipolar system can system’s metallic return is connected to ground. Therefore, the PPF is selected to be investigated in be equivalent to the PPF given bipolar system’s metallic return is connected to ground. Therefore, the this study, especially in terms of fault current. Fault current propagation can be segmented into SM PPF is selected to be investigated in this study, especially in terms of fault current. Fault current capacitor discharging before blocking IGBT, decayed freewheeling current, and AC gird in-feed current propagation can be segmented into SM capacitor discharging before blocking IGBT, decayed after blocking IGBT. Before blocking IGBT, the discharging capacitor in inserted SMs leads to surge freewheeling current, and AC gird in-feed current after blocking IGBT. Before blocking IGBT, the current, which provides a high electrical pressure on semiconductor devices. Thus, from a protection discharging capacitor in inserted SMs leads to surge current, which provides a high electrical perspective, IGBT is blocked with a control signal when the arm current reaches the threshold value. pressure on semiconductor devices. Thus, from a protection perspective, IGBT is blocked with a control signal when the arm current reaches the threshold value. 2.2.1. Submodule Capacitor Discharging Period At the beginning of the PPF, the capacitor in every inserted SM discharges and bridge arm current 2.2.1. Submodule Capacitor Discharging Period surges. Figure 3 depicts the fault current circuit, in which the capacitor discharging current ﬂows At the beginning of the PPF, the capacitor in every inserted SM discharges and bridge arm through the IGBT of the inserted SMs and the anti-parallel diode of the removed SMs in each converter current surges. Figure 3 depicts the fault current circuit, in which the capacitor discharging current unit. The fault occurs at point A and point B, which are connected with dashed line in Figure 3. flows through the IGBT of the inserted SMs and the anti-parallel diode of the removed SMs in each Considering that converter includes six arms with same topology, hence, only the upper arm of phase converter unit. The fault occurs at point A and point B, which are connected with dashed line in A is shown with insert SMs and removed SMs due to the space of ﬁgure and simplicity. All the IGBT Figure 3. Considering that converter includes six arms with same topology, hence, only the upper can be turned o as the bridge arm current reaches the threshold value to protect the IGBT from arm of phase A is shown with insert SMs and removed SMs due to the space of figure and simplicity. overcurrent damage. The voltage cross converter unit v decreases with SM capacitor discharging conv All the IGBT can be turned off as the bridge arm current reaches the threshold value to protect the until the IGBT is blocked. In contrast to the two-level VSC-HVDC system under the PPF, in which a IGBT from overcurrent damage. The voltage cross converter unit 𝑣 decreases with SM capacitor large capacitor connected to the DC side discharges to zero, even if IGBT is blocked (assuming the discharging until the IGBT is blocked. In contrast to the two-level VSC-HVDC system under the PPF, resistance in fault circuit R < 2 L /C ), the voltage of the SM capacitor is normally maintained eq eq eq in which a large capacitor connected to the DC side discharges to zero, even if IGBT is blocked given the blocked IGBTs in the MMC-HVDC system. If v is higher than the AC grid line voltage conv (assuming the resistance in fault circuit 𝑅 <2 𝐿 /𝐶 ), the voltage of the SM capacitor is v (j indicates phases a, b, and c), then the AC grid current cannot be fed in the fault current loop. s j_line normally maintained given the blocked IGBTs in the MMC-HVDC system. If 𝑣 is higher than the If V is lower than the AC grid line voltage, then the AC grid begins to feed the AC current i (j conv s j AC grid line voltage 𝑣 (j indicates phases a, b, and c), then the AC grid current cannot be fed in indicates phases a, b, and c) into the fault current loop. In Figure 3, the red dashed line indicates the the fault current loop. If 𝑉 is lower than the AC grid line voltage, then the AC grid begins to feed the AC current 𝑖 (j indicates phases a, b, and c) into the fault current loop. In Figure 3, the red Appl. Sci. 2019, 9, x 6 of 26 Appl. Sci. 2019, 9, x 6 of 26 Appl. Sci. 2019, 9, 1661 6 of 26 dashed line indicates the fault currents 𝑖 fed from the AC grid; these fault currents are equally dashed line indicates the fault currents 𝑖 fed from the AC grid; these fault currents are equally divided into an upper arm current 𝑖 and a lower arm current 𝑖 (not marked in the figure fault currents i fed from the AC grid; these fault currents are equally divided into an upper arm divided into an upper arm current 𝑖 _ and a lower arm current 𝑖 _ (not marked in the figure s j _ _ due to complexity). The blue dashed–dotted line represents the capacitor discharging path, and 𝑖 current i and a lower arm current i (not marked in the ﬁgure due to complexity). The blue due to complexity). The blue dashed–dotted line represents the capacitor discharging path, and 𝑖 p j_ac n j_ac dashed–dotted expresses the disch line r aepr rging esents arm cur the capacitor rents. Both AC dischar fee ging dingpath, current in and i red expr and esses SM c the apac dischar itor diging scharg arm ing expresses the discharging arm currents. Both AC feeding current in red c j and SM capacitor discharging current in blue flow through inserted SMs and removed SMs in each arm. Specifically, the fault currents. Both AC feeding current in red and SM capacitor discharging current in blue ﬂow through current in blue flow through inserted SMs and removed SMs in each arm. Specifically, the fault inserted current flow SMs and s through removed fre SMs ewheeling in each diode in remo arm. Speciﬁcally ved SMs and , the fault curr cap enta ﬂows citor an thrd ough on-state freewheeling IGBT in current flows through freewheeling diode in removed SMs and capacitor and on-state IGBT in inserted SMs, shown in Figure 3. The equivalent circuits of the two fault current paths are exhibited diode in removed SMs and capacitor and on-state IGBT in inserted SMs, shown in Figure 3. The inserted SMs, shown in Figure 3. The equivalent circuits of the two fault current paths are exhibited in Figure 4a,b. However, the AC feeding current can be ignored in comparison with the capacitor equivalent circuits of the two fault current paths are exhibited in Figure 4a,b. However, the AC feeding in Figure 4a,b. However, the AC feeding current can be ignored in comparison with the capacitor discharging current during this period. current can be ignored in comparison with the capacitor discharging current during this period. discharging current during this period. Phase-B Phase-C i i i pa Phase-B Phase-C T i A pa pb i pc i T A 1 D pb pc upper arm upper arm i dc1 Inserted 1 D C 1 upper arm upper arm dc1 Inserted 1 C 0 SMs SMs T T i i i 2 D 2 i ca i cb i cc D 2 ca cb cc v 2 conv conv 1 D Removed D 1 Removed SMs SMs T 2 D 2 2 C uv > uv sa _ line> convL L L Pole-to- sa sa _ line conv L L L Pole-to- sa 0 0 L 0 0 0 pole Fault uv > L i i i pole Fault uv sb _ line> conv L sb sa i i na sb sa sb _ line conv sb na sb i i uv > L i nb i sc uv sc _ line> conv L sc nb sc sc _ line conv sc nc nc L 0 L 0 0 Phase-A Phase-B Phase-C Phase-A Phase-B Phase-C lower arm lower arm lower arm lower arm lower arm lower arm Figure 3. Direct current pole-to-pole fault circuit diagram before blocking submodules Figure 3. Direct current pole-to-pole fault circuit diagram before blocking submodules Figure 3. Direct current pole-to-pole fault circuit diagram before blocking submodules. i pa _ ac L R pa _ ac u L R L dc R dc C i i dis u L R dc dc sa sa sa C eq i sa dis sa sa sa sa eq i i L 0 i na _ ac i dis 0 i i i na _ ac R dis L i i i ca cb cc R dc L dc ca cb cc dc dc − + i + pb _ ac pb _ ac I + u L R i + C C I u sb L sb R sb C dis0 i sb sb sb sb C eqa C eqb C eqc dis0 sb i R L eqa eqb eqc i nb _ ac R L 0 eq nb _ ac R R 0 eq R fault R fault − fault fault − L R 2 L i pc _ ac 2 L 2 L L dc R dc − + pc _ ac 2 L 2 L 2 L 0 dc dc 0 0 − + u L R i 0 0 0 L sc i sc u sc R sc sc sc sc sc L R L dc R dc L i L dc dc eq i nc _ ac L 0 nc _ ac 0 eq (a) (b) (c) (a) (b) (c) Figure 4. (a) Equivalent AC grid feeding current circuit, (b) equivalent SM capacitor discharging Figure 4. (a) Equivalent AC grid feeding current circuit, (b) equivalent SM capacitor discharging Figure 4. (a) Equivalent AC grid feeding current circuit, (b) equivalent SM capacitor discharging current circuit, (c) simplified SM capacitor discharging current circuit. current circuit, (c) simpliﬁed SM capacitor discharging current circuit. current circuit, (c) simplified SM capacitor discharging current circuit. 2C The equivalent phase capacitor C demonstrated in Figure 4b is normally considered in the eq existing references [5,6,15,17]. However, Referπ ence [36] proposed that the calculation value of the 4.42 （， 4.4194） 4.42 C （， 4.4194） 1.4 C 0 0 fault current with C = is close to the simulation value. Furthermore, C is obtained as for eq eq N N the optimal approximation of the discharging current via a tracing point method [37]. Consequently, 4.4 4.4 Reference [38] veriﬁed that C of the three converter units depends on the fault time t and modulation eq f ratio m, as expressed in Equation (1). Thus, the selection of fault time t and modulation ratio m should 4.38 4.38 be reconsidered in this paper. Based on equivalent capacitor expression in Equation (2), the relationship between discharging coecient and time is shown in Figure 5, given the preset modulation ratio 4.36 4.36 （， 4.3536）（， 4.3536） m (0.93) of test system. From the perspective of fault protection, the most serious situation must be considered in selecting t . According to the red curve in Figure 5, the maximum discharging coecient 4.34 4.34 0 k 0.002 0.004 0.006 0.008 0.01 0 0.002 0.004 0.006 0.008 0.01 is obtained when t = , k = 0, 1, 2:::. Namely, the maximum C equals 1.473, since the fault time eq Time(s) Time/s Ti Tim me e(/s s) of the simulation is set at 1.2 s. Figure 5. Relationship between discharging coefficient and fault time (m = 0.93). Figure 5. Relationship between discharging coefficient and fault time (m = 0.93). 2C 2C 2C 0 0 0 C = + + (1) eq 2 2 2 2 2 2 2 2 [1 + m sin (!t)]N [1 + m sin (!t )]N [1 + m sin (!t + )]N 3 3 Discharging coefficient Discharging coefficient Appl. Sci. 2019, 9, x 6 of 26 dashed line indicates the fault currents 𝑖 fed from the AC grid; these fault currents are equally divided into an upper arm current 𝑖 and a lower arm current 𝑖 (not marked in the figure _ _ due to complexity). The blue dashed–dotted line represents the capacitor discharging path, and 𝑖 expresses the discharging arm currents. Both AC feeding current in red and SM capacitor discharging current in blue flow through inserted SMs and removed SMs in each arm. Specifically, the fault current flows through freewheeling diode in removed SMs and capacitor and on-state IGBT in inserted SMs, shown in Figure 3. The equivalent circuits of the two fault current paths are exhibited in Figure 4a,b. However, the AC feeding current can be ignored in comparison with the capacitor discharging current during this period. Phase-B Phase-C pa i T A pb pc i 1 D upper arm upper arm dc1 Inserted 1 C SMs 2 i i i ca cb cc v 2 conv Removed 1 SMs 2 C uv > L L Pole-to- sa _ line conv sa L 0 0 pole Fault uv > L i i i sb _ line conv sb sa na sb i i uv > L nb sc sc _ line conv sc nc L L 0 0 Phase-A Phase-C Phase-B lower arm lower arm lower arm Figure 3. Direct current pole-to-pole fault circuit diagram before blocking submodules pa _ ac L R u L dc dc C i dis sa sa sa sa eq na _ ac i i i dis L ca cb cc dc dc pb _ ac I + u L R sb sb C C C dis0 sb sb eqa eqb eqc i R nb _ ac eq R R fault fault − L R pc _ ac 2 L 2 L 2 L − + dc dc 0 0 0 L i u R sc sc sc sc L R dc dc L i L nc _ ac 0 eq Appl. Sci. 2019, 9, 1661 7 of 26 (a) (b) (c) Figure 4. (a) Equivalent AC grid feeding current circuit, (b) equivalent SM capacitor discharging C = (2) eq current circuit, (c) simplified SM capacitor discharging current circuit. 4.42 （， 4.4194） 4.4 4.38 4.36 （， 4.3536） 4.34 0 0.002 0.004 0.006 0.008 0.01 Ti Tim me e(/s s) Figure Figure 5. 5. Relationship Relationship betwee betweenn dis dischar charg ging ing coe coe fficient and f cient and fault ault time (m = time (m = 0.93). 0.93). During the SM capacitor discharging period, the AC feeding current can be ignored, because the discharging current is dominant. For example, the Phase-A discharging circuit can be regarded as a second-order RLC circuit (circuit consisting of a resistor, an inductor and a capacitor), as displayed in Figure 4c. Here, the resistance in the arms is neglected. The initial voltage and current of the capacitor discharging circuit are expressed by Equations (3) and (4), respectively. u (0 ) = u (0 ) = U (3) c + c dc du i (0 ) = i (0 ) = C = I (4) dis + dis eq dis0 dt The equivalent capacitor, inductance, and resistance presented in Figure 4c are obtained as follows: C = (5) eq L = L + 2L (6) eq 0 dc R = R + 2R (7) eq f ault dc The second-order equation of the RLC circuit is expressed in Equation (8) as follows: d i eq di 1 dis dis + + i = 0 (8) dis dt L dt L C eq eq eq t eq I ! dis0 0 i (t) = e [U sin(! t) sin(! t )] (9) dis dc 1 1 L ! eq 1 2L 2( L + 2L ) eq 0 dc = = (10) R 2R + R eq dc f ault 1 eq ! = (11) L C 2L eq eq eq ! = (12) L C eq eq = arctan(!) (13) Discharging coefficient Appl. Sci. 2019, 9, 1661 8 of 26 where is the attenuation coecient of the capacitor discharging current, ! is the oscillating current angular frequency, ! is the inherent angular frequency of the circuit, and is the initial phase angle of the initial current. The capacitor discharges until the capacitor voltage decreases to 0. The maximum discharging current can be obtained at t without blocking IGBT. dis_peak 1 U eq dc t = arctan( ) (14) dis_peak ! I L 0 dis0 eq dis_peak C I ! L eq 0 eq dis0 dc I = e (U + ) (15) dis_peak dc 2 2 2 2 L U eq I ! L + U dc eq dis0 dc The AC side can be considered a three-phase short-circuit fault under the DC pole-to-pole fault, and the DC fault current only consists of the discharging currents of the three converter units, given the balance fault on the AC side. Thus, the fault current through DC line is deﬁned as i (t) = i (t) (16) dc dis For example, Phase-A arm current during this period can be decomposed using Equations (17) and (18). 1 1 i (t) = i (t) + i (t) (17) pa sa dc 3 2 1 1 i (t) = i (t) i (t) (18) na dc sa 3 2 The Phase-A voltage on the AC side is set as u = 2U sin(! t + ) (19) sa s s a where is the phase angle (taken as 0 for convenience in calculation afterward), and ! is the a s fundamental angular frequency. Then, the Phase-A current can be obtained using Equation (20). 2U i = sin(! t + ') (20) sa s a eq where ' is the impedance angle. The AC feeding current in each phase is equally divided into upper and lower arms. 1 2U i (t) = i (t) = sin(! t + ') (21) pa_ac na_ac s a 2 Z eq Z = R + ! L + L (22) eq s s 0 sa L + L sa 0 '= arctan( ) (23) sa In accordance with Equations (9), (16)–(18), and (21), the expression of the Phase-A arm current can be obtained. 1 t eq I ! 1 2U dis0 0 s i = e [U sin(! t) sin(! t )] + sin(! t + ') (24) pa s a dc 1 1 3 L ! 2 Z eq eq t I ! 1 eq 1 2U 0 s dis0 i = e [U sin(! t) sin(! t )] sin(! t + ') (25) na dc 1 1 s a 3 L ! 2 Z eq 1 eq Appl. Sci. 2019, 9, 1661 9 of 26 2.2.2. Freewheeling Current and AC Feeding Current Period Appl. Sci. 2019, 9, x 9 of 26 The fault current circuit after completely discharging IGBT blocks or capacitor to V = 0 is conv Appl. Sci. 2019, 9, x 9 of 26 depicted in Figure 6, in which the red dotted line indicates the AC feeding current, and the blue dash-dotted line represents the freewheeling current given 1 the stored energy in the arm reactors. The LL + sa 0 equivalent circuits of the AC feeding and freewheeling DC currents are illustrated in Figure 7a,b, 2 (23) ϕ =arctan( ) LL + sa 0 respectively. The fault current can be considered a superposition of the three-phase short-circuit fault sa 2 (23) ϕ =arctan( ) and decayed freewheeling currents. Thus, the fault currents in the upper and lower arms can be sa In accordance with Equations (9), (16)–(18), and (21), the expression of the Phase-A arm current deﬁned as can be obtained. In accordance with Equations (9), (16)–(18), and (21), the expression of the Phase-A arm current i = i + i (26) p j p j_ac f w j can be obtained. 11IU ω 2 eq dis00 s i = i i (27) ie=− [U sin(ωω t) sin( t−θ )]+ sin(ωt+θ− ϕ ) n j f w j n j_ac (24) pa dc 11 sa 32 −LZ C ω 11IU ω 2 eq 1 eq eq dis00 s ie=− [U sin(ωω t) sin( t−θ )]+ sin(ωt+θ− ϕ ) (24) pa dc 11 sa where i denotes the freewheeling current in each converter phase. i and i indicate the AC f w j p j_ac n j_ac 32LZ ω eq 1 eq feeding current via the upper and lower arms of each phase, respectively. The analysis during the SM − C 11IU ω 2 eq dis00 s capacitor discharging period shows that the initial freewheeling current is equal to the peak value of ie=− [U sin(ωω t ) sin( t−θ )]− sin(ωt+θ− ϕ ) (25) na dc 11 sa 32LZ C ω 11IU ω 2 eqeq 1 eq dis00 s the discharging current in each converter phase. ie=− [U sin(ωω t ) sin( t−θ )]− sin(ωt+θ− ϕ ) (25) na dc 11 sa 32LZ ω eq 1 eq I = I (28) 2.2.2. Freewheeling Current and AC Feeding C f w0urrent dis Period _peak 2.2.2. Freewheeling Current and AC Feeding Current Period i T Phase-B Phase-C pb pa 1 D A pc C dc 2 upper arm upper arm i T Phase-B Phase-C D pb A pa 1 i pc T 1 C upper arm dc 2 D upper arm 2 0 i v fwb fwc fwa Blocked conv 2 i i T i SMs fwc v 1 fwb D fwa conv Blocked SMs 1 D 2 C uv > L D 2 C L L Pole-to- sa _ line conv sa 2 L 0 0 pole Fault uv > uv > LL sa _ line conv L L Pole-to- sa sb _ line conv sb sa L 0 0 pole Fault uv > L i i uv > L i i sb _ line conv sb sc _ line conv sc sa na sb nb nc uv > L i i i i L na L sc _ line conv sc sb nb sc nc sc 0 0 Phase-A Phase-B Phase-C lower arm lower arm lower arm Phase-A Phase-B Phase-C lower arm lower arm lower arm Figure 6. Diagram of the DC pole-to-pole fault circuit after blocking SMs. Figure 6. Diagram of the DC pole-to-pole fault circuit after blocking SMs. Figure 6. Diagram of the DC pole-to-pole fault circuit after blocking SMs. pa _ ac i L R u L R fw dc dc sa sa sa sa i L pa _ ac 0 na _ ac i i L R i i R fwc u L R L fwa fwb i fw dc dc dc sa sa sa dc sa pb _ ac 0 na _ ac i i i u L R i R I fwa I I fwc L fwb sb sb sb sb dc fw 0 fw 0 fw 0 dc i i nb pb _ a _cac R fault u L R fault i I I I sb sb sb fw 0 fw 0 fw 0 sb i L nb _ ac L R 2L R pc _ ac 0 2L 2L dc dc R 0 0 0 fault u L R i fault sc sc sc sc L R L R 2L dc i L 2L 2L dc pc _ ac dc dc nc _ ac 0 0 0 0 L i u R sc sc sc sc dc dc i L nc _ ac (a) (b) (a) (b) Figure 7. Equivalent circuit of the (a) AC feeding current and (b) freewheeling DC current. Figure 7. Equivalent circuit of the (a) AC feeding current and (b) freewheeling DC current. Figure 7. Equivalent circuit of the (a) AC feeding current and (b) freewheeling DC current. The fault current circuit after completely discharging IGBT blocks or capacitor to 𝑉 =0 is depicted in Figure 6, in which the red dotted line indicates the AC feeding current, and the blue dash- The fault current circuit after completely discharging IGBT blocks or capacitor to 𝑉 =0 is dotted line represents the freewheeling current given the stored energy in the arm reactors. The depicted in Figure 6, in which the red dotted line indicates the AC feeding current, and the blue dash- equivalent circuits of the AC feeding and freewheeling DC currents are illustrated in Figure 7a and dotted line represents the freewheeling current given the stored energy in the arm reactors. The Figure 7b, respectively. The fault current can be considered a superposition of the three-phase short- equivalent circuits of the AC feeding and freewheeling DC currents are illustrated in Figure 7a and Figure 7b, respectively. The fault current can be considered a superposition of the three-phase short- Appl. Sci. 2019, 9, 1661 10 of 26 Thus, the freewheeling current of each arm and the DC line current can be obtained using Equations (29) and (30). i (t) = I e (29) f w j f w0 i (t) = 3I e (30) dc f w0 For example, the initial arm current of the freewheeling period of Phase A is expressed as follows: I = I + i (t ) (31) pa_bk f w0 sa dis_peak I = I i (t ) (32) sa na_bk f w0 dis_peak Similarly, the arm currents can be decomposed as Equations (33) and (34). i (t) = i (t) + i (t) (33) pa f wa pa_ac i (t) = i (t) i (t) (34) na f wa na_ac In reference to Equations (21) and (28), the arm currents can be deﬁned as 1 1 2U i (t) = I e + sin(! t + ') (35) pa dis_peak s a 3 2 Z eq 1 1 2U i (t) = I e sin(! t + ') (36) na dis_peak s a 3 2 Z eq 2(2L +2L ) 0 dc = (37) 2R + R dc f ault where is the attenuation coecient of the freewheeling current. Equivalent impedance is expressed in Equation (22), and the peak value of the discharging current can be obtained via Equation (15). 2.3. Simulation Veriﬁcation The analyses of the arm and DC line currents have been veriﬁed via a simulation. The monopolar MMC-HVDC system is adopted in this study, and the model parameters are listed in Table 1. The rectiﬁer side takes DC voltage and active power control, and the inverter side adopts active and reactive power controls. The protection action, including blocking IGBTs, is disregarded in the simulation to investigate the natural response to a fault. A completely discharged SM capacitor can be equivalent to blocking IGBTs at t . The comparison between the calculation and the simulation in terms of dis_peak DC line and arm currents (Phase-A upper arm) is depicted in Figures 8 and 9, respectively. Figure 8 demonstrated that the DC line current increases to a high level in a few milliseconds. The IGBTs must be blocked rapidly due to the electrical pressure on the DC line. The DC line current decays after completely discharging the SM capacitor. Similarly, the arm current accelerates during the discharging period (Figure 9) but involves the AC feeding component after completely discharging the SM capacitor at 1.213 s. The dierence between the simulation and calculation values in the arm current before 1.213 s may be attributed to the imbalance shunt current among the converter units. In addition, the initial AC current at fault time (1.2 s) is ignored in the calculation, thereby leading to more or less error. However, the overall accuracy of the calculation analysis can be accepted for fault study on the basis of the general consistency between the simulation and calculation curves in Figures 8 and 9. Appl. Sci. 2019, 9, x 11 of 26 Appl. Sci. 2019, 9, x 11 of 26 rectifier side takes DC voltage and active power control, and the inverter side adopts active and rectifier side takes DC voltage and active power control, and the inverter side adopts active and reactive power controls. The protection action, including blocking IGBTs, is disregarded in the reactive power controls. The protection action, including blocking IGBTs, is disregarded in the simulation to investigate the natural response to a fault. A completely discharged SM capacitor can simulation to investigate the natural response to a fault. A completely discharged SM capacitor can be equivalent to blocking IGBTs at 𝑡 . The comparison between the calculation and the be equivalent to blocking IGBTs at 𝑡 _ . The comparison between the calculation and the simulation in terms of DC line and arm currents (Phase-A upper arm) is depicted in Figure 8 and 9, simulation in terms of DC line and arm currents (Phase-A upper arm) is depicted in Figure 8 and 9, respectively. Figure 8 demonstrated that the DC line current increases to a high level in a few respectively. Figure 8 demonstrated that the DC line current increases to a high level in a few milliseconds. The IGBTs must be blocked rapidly due to the electrical pressure on the DC line. The milliseconds. The IGBTs must be blocked rapidly due to the electrical pressure on the DC line. The DC line current decays after completely discharging the SM capacitor. Similarly, the arm current DC line current decays after completely discharging the SM capacitor. Similarly, the arm current accelerates during the discharging period (Figure 9) but involves the AC feeding component after accelerates during the discharging period (Figure 9) but involves the AC feeding component after completely discharging the SM capacitor at 1.213 s. The difference between the simulation and completely discharging the SM capacitor at 1.213 s. The difference between the simulation and calculation values in the arm current before 1.213 s may be attributed to the imbalance shunt current calculation values in the arm current before 1.213 s may be attributed to the imbalance shunt current among the converter units. In addition, the initial AC current at fault time (1.2 s) is ignored in the among the converter units. In addition, the initial AC current at fault time (1.2 s) is ignored in the calculation, thereby leading to more or less error. However, the overall accuracy of the calculation calculation, thereby leading to more or less error. However, the overall accuracy of the calculation analysis can be accepted for fault study on the basis of the general consistency between the simulation analysis can be accepted for fault study on the basis of the general consistency between the simulation and calculation curves in Figure 8 and 9. and calculation curves in Figure 8 and 9. Appl. Sci. 2019, 9, 1661 11 of 26 Table 1. Parameters of the modular multilevel converter-based high-voltage direct current system’s Table 1. Parameters of the modular multilevel converter-based high-voltage direct current system’s Table 1. Parameters of the modular multilevel converter-based high-voltage direct current system’s simulation model. simulation model. simulation model. System Parameters System Parameters System Parameters DC voltage ± 420 kV SM number (2 N) 60 DC voltage ± 420 kV SM number (2 N) 60 Rated power 1250 MW Arm inductance 140 mH DC voltage 420 kV SM number (2 N) 60 Rated power 1250 MW Arm inductance 140 mH Rated power 1250 MW Arm inductance 140 mH Short-circuit ratio 20 Internal grounding Yg Short-circuit ratio 20 Internal grounding Yg Short-circuit ratio 20 Internal grounding Yg AC voltage 450 kV AC line length 10 km AC voltage 450 kV AC line length 10 km AC voltage 450 kV AC line length 10 km Frequency 50 Hz Line resistance 12.73m/ Ω km Frequency 50 Hz Line resistance 12.73m/ Ω km Frequency 50 Hz Line resistance 12.73 mW/km Transformer voltage 525 kV/450 kV Line inductance 0.9937 mH T Trans ransformer formevoltage r voltage 525 525 kV/ kV/450 45kV 0 kV Line Line induct inductance ance 0.9937 0.9937 mH mH TTransformer ransformer grounding grounding Yn Yn/yn /yn Line Line c capacitance apacitance 12.74 12.74 n nF/km F/km Transformer grounding Yn/yn Line capacitance 12.74 nF/km Smoothing inductance 20 mH DC line length 200 km Smoothing inductance 20 mH DC line length 200 km Smoothing inductance 20 mH DC line length 200 km x 10 x 10 simulation value simulation value calculation value(discharging) calculation value(discharging) calculation value(freewheeling) calculation value(freewheeling) ts = 1.213 ts dis _ peak= 1.213 dis _ peak 1.2 1.22 1.24 1.26 1.28 1.3 1.2 1.22 1.24 1.26 1.28 1.3 Ti Tim me e( /s s) Time/s Time(s) Figure 8. Simulation and calculation values of the DC line current. Figure Figure 8. 8. Sim Simulation ulation an and d cal calculation culation va values lues o of f th the e DC DC l line ine cu curr rren ent. t. x 10 x 10 calculation value(discharging) calculation value(discharging) calculation value(freewheeeling+AC feeding) calculation value(freewheeeling+AC feeding) simulation value 1.5 simulation value 1.5 0.5 0.5 ts = 1.213 ts dis _ peak= 1.213 dis _ peak 1.2 1.22 1.24 1.26 1.28 1.3 1.2 1.22 1.24 1.26 1.28 1.3 Ti Time(s me/s) Ti Time(s me/s) Figure Figure 9. 9. Simulation Simulationand andcalculation calculation v values aluesof of the the arm current (Phase-A upper arm). arm current (Phase-A upper arm). Figure 9. Simulation and calculation values of the arm current (Phase-A upper arm). 2.4. Protection Demand The MMC-HVDC system focuses on the protection and healthy part safety of the converter station. Speciﬁcally, the IGBTs are regarded as important components in the converter station given their high cost but low electrical withstanding ability. IGBTs and freewheeling diodes are destroyed due to overheating under extremely high arm current. Another point in protection relaying is that the DCCB occupies a large portion of the cost in the HVDC project considering its high interruption capacity. Therefore, the arm and DC line currents under a fault must be investigated, and the limitation of fault current methods is required to satisfy protection demands. In accordance with the fault current analysis discussed in Section 2, the anti-parallel diodes in removed SMs and IGBTs in inserted SMs experience a dramatic overcurrent before blocking IGBTs. Moreover, the diode D in inserted SMs can withstand the peak value of the discharging current when the IGBTs T are blocked; this issue is considered an essential challenge to the DC fault protection of the MMC-HVDC system [4]. Considering the action of blocking IGBTs, the arm current under the DC pole-to-pole fault has been simulated (Figure 10). Using Equations (16) and (28), the DC current reaches 30 kA when the Phase- A Ar m uppe curr r ar enm c t(Au ) rrent/A Phase- A Ar m uppe curr r ar enm c t(Au ) rrent/A DC Current(A) DC current/A DC Current(A) DC current/A Appl. Sci. 2019, 9, x 12 of 26 2.4. Protection Demand The MMC-HVDC system focuses on the protection and healthy part safety of the converter station. Specifically, the IGBTs are regarded as important components in the converter station given their high cost but low electrical withstanding ability. IGBTs and freewheeling diodes are destroyed due to overheating under extremely high arm current. Another point in protection relaying is that the DCCB occupies a large portion of the cost in the HVDC project considering its high interruption capacity. Therefore, the arm and DC line currents under a fault must be investigated, and the limitation of fault current methods is required to satisfy protection demands. In accordance with the fault current analysis discussed in Section 2, the anti-parallel diodes in removed SMs and IGBTs in inserted SMs experience a dramatic overcurrent before blocking IGBTs. Moreover, the diode 𝐷 in inserted SMs can withstand the peak value of the discharging current when the IGBTs 𝑇 are blocked; this issue is considered an essential challenge to the DC fault protection of the MMC-HVDC system [4]. Considering the action of blocking IGBTs, the arm current under the DC pole-to-pole fault has Appl. Sci. 2019, 9, 1661 12 of 26 been simulated (Figure 10). Using Equations (16) and (28), the DC current reaches 30 kA when the IGBT is blocked beyond the maximum interruption capacity of 16 kA [33]. When a fault occurs, the arm current mainly consists of the capacitor discharging and AC feeding currents in the initial stage. IGBT is blocked beyond the maximum interruption capacity of 16 kA [33]. When a fault occurs, the Specifically, the SM capacitor begins to discharge the current through arms and DC loops, and the arm current mainly consists of the capacitor discharging and AC feeding currents in the initial stage. IGBTs are blocked with a triggering signal while the arm current reaches the threshold value. The Speciﬁcally, the SM capacitor begins to discharge the current through arms and DC loops, and the IGBT blocking time is set to 1.205 s, that is, 5 ms after fault occurrence to provide a distinguishable IGBTs are blocked with a triggering signal while the arm current reaches the threshold value. The IGBT vision on the current development; this timeframe is slightly longer than that in the real project (2– blocking time is set to 1.205 s, that is, 5 ms after fault occurrence to provide a distinguishable vision on 3ms). In addition, the AC side begins to feed current into the fault current circuit while a fault occurs the current development; this timeframe is slightly longer than that in the real project (2–3 ms). In because the rated AC line voltage is set to more than half of the DC voltage (𝑉 = 450𝑘𝑉, 𝑉 = addition, the AC side begins to feed current into the fault current circuit while a fault occurs because ±420𝑘𝑉 ). However, if 𝑉 < 𝑉 =0.5𝑈 , then the AC feeding current will appear as 𝑉 > _ _ the rated AC line voltage is set to more than half of the DC voltage (V = 450 kV, V = 420 kV). AC_line DC 𝑉 given the SM capacitor’s discharging effect. In Figure 10, the AC feed current (red line) in the However, if V < V = 0.5U , then the AC feeding current will appear as V > V given DC DC DC AC_line AC_line three-phase uncontrolled rectifier bridge, and the energy stored in the arm reactors begin to freewheel the SM capacitor ’s discharging eect. In Figure 10, the AC feed current (red line) in the three-phase decayed current (blue line) through anti-parallel diodes because the IGBTs are blocked. The AC uncontrolled rectiﬁer bridge, and the energy stored in the arm reactors begin to freewheel decayed circuit breaker (ACCB) is triggered to isolate the fault section after a fault is detected. The delay in current (blue line) through anti-parallel diodes because the IGBTs are blocked. The AC circuit breaker the ACCB is normally 4–5 cycles. Thus, the triggering time point is set to 100 ms after the fault (ACCB) is triggered to isolate the fault section after a fault is detected. The delay in the ACCB is occurrence. Figure 10 demonstrates that the arm current reaches approximately 10 kA while the IGBT normally 4–5 cycles. Thus, the triggering time point is set to 100 ms after the fault occurrence. Figure 10 blocks and decays slowly with the AC feeding component. The limitation of the fault current is demonstrates that the arm current reaches approximately 10 kA while the IGBT blocks and decays essential to realize protection considering the limitation in the DCCB capability. The AC feeding slowly with the AC feeding component. The limitation of the fault current is essential to realize current can be restrained using a parallel-connected thyristor in previous works [18–21]. Therefore, protection considering the limitation in the DCCB capability. The AC feeding current can be restrained the discharging current limitation and rapid decaying freewheeling current are the focus in the using a parallel-connected thyristor in previous works [18–21]. Therefore, the discharging current present study. limitation and rapid decaying freewheeling current are the focus in the present study. AC feeding current Capacitor discharging current & reactor freewheeling current Arm current (phase-A upper arm) -2000 Fault occurence IGBT blocked（1.205s) ACCB triggered -4000 1.18 1.2 1.22 1.24 1.26 1.28 1.3 1.32 Time(s) Figure 10. Phase-A upper arm current under the DC pole-to-pole fault. Figure 10. Phase-A upper arm current under the DC pole-to-pole fault. 3. Enhanced Fault Current Limiting Circuit 3. Enhanced Fault Current Limiting Circuit 3.1. Fault Current-Limiting Characteristics 3.1. Fault Current-Limiting Characteristics The FCLC mainly consists of energy dissipation resistance and limiting inductance [14,15,25,35]. Thus, investigating the inﬂuence of the two elements on the fault current development is important. The related simulation was performed under controlled conditions. Figure 11a displays that limiting inductance can help slow down the accelerating speed of the fault current but increase the time spent in decaying the freewheeling current to its expected level. In Figure 11b, the energy dissipation resistance facilitates the constraining fault current peak value and the accelerating extinguishment of the freewheeling current. The adoption of the reactor and resistance in the discharging period is suitable, considering that the maximum fault current will ﬂow through the freewheeling diode while the IGBTs are blocked or the SM capacitors are completely discharged. However, the limiting inductance can aect the dynamic response speed and prolong the recovery time. Therefore, further study on the FCLC design is required. A series of simulations was conducted under controlled conditions to obtain the expected fault current limitation and rapid recovery. The simulation conditions are divided into resistance and reactor groups as follows: the former is labeled with “a”, “b”, “c”, and “d”, and the latter with “e”, “f”, “g”, and “h”. Speciﬁcally, the related explanations of the conditions are listed in Table 2. “X” indicates that Arm current(A) Appl. Sci. 2019, 9, 1661 13 of 26 Appl. Sci. 2019, 9, x 13 of 26 the resistance or reactor is inserted in the fault circuit, and “” denotes the absence of resistance or The FCLC mainly consists of energy dissipation resistance and limiting inductance [14,15,25,35]. reactor. First, the reactor was ignored, and Figure 12a illustrates that the red curve (“ag”) provides an Thus, investigating the influence of the two elements on the fault current development is important. improved performance in limiting fault current. Thus, the condition with “a” was selected for the The related simulation was performed under controlled conditions. Figure 11a displays that limiting following simulation. Figure 12b depicts the performance of various reactor-based FCLC scheme, in inductance can help slow down the accelerating speed of the fault current but increase the time spent which the red dashed–dotted curve (“ad”) represents the lowest fault current level. However, the “ad” in decaying the freewheeling current to its expected level. In Figure 11b, the energy dissipation scheme was unsatisfactory for real projects, where large inductance will aect the dynamic response resistance facilitates the constraining fault current peak value and the accelerating extinguishment of speed of the entire system during the normal state. Therefore, the “af” scheme most closely approaches the freewheeling current. The adoption of the reactor and resistance in the discharging period is the optimized FCLC scheme, because the energy dissipation resistance consumes the energy in the suitable, considering that the maximum fault current will flow through the freewheeling diode while Appl. Sci. 2019, 9, x 13 of 26 fault circuit. This phenomenon is due to the fault being detected, and the FCL reactor being inserted to the IGBTs are blocked or the SM capacitors are completely discharged. However, the limiting limit the increase in current speed, but also being removed to accelerate the decaying speed of the inductance can affect the dynamic response speed and prolong the recovery time. Therefore, further The FCLC mainly consists of energy dissipation resistance and limiting inductance [14,15,25,35]. study on freewheeling the FCLC des current i after gn is r blocking equired. the IGBT. Thus, investigating the influence of the two elements on the fault current development is important. The related simulation was performed under controlled conditions. Figu 4 re 11a displays that limiting 4 x 10 x 10 inductance can help slow down the accelerating speed of the fault current but increaNon se the ti e me spent None 6 L=20mH R=0.05ohm in decaying the freewheeling current to its expected level. In Figure 11b, the energy dissipation R=0.05ohm L=20mH R=0.05ohm L=20mH 5 R=0.5ohm L=20mH R=0.05ohm L=100mH resistance facilitates the constraining fault current peak value and the accelerating extinguishment of x 10 R=5ohm L=20mH 4 4 R=0.05ohm L=200mH the freewheeling current. The adoption of the reactor and resistance in the discharging period is 3 3 x 10 suitable, considering that the maximum fault current wil1l flow through the freewheeling diode while 2 2 1.2 1.205 the IGBTs 1 are blocked or the SM capacitors are completely discharged. However, the limiting 0 0 inductance can affect the dynamic response speed and prolong the recovery time. Therefore, further 1.2 1.205 Fault occurrence Fault occurrence -1 -1 study on 1.1 the 1.2 FCLC des 1.3 1.i 4gn is r 1.5 equir 1.6 ed. 1.7 1 1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8 Time(s) Time(s) 4 x 10 x 10 (a) ( b) None None 6 L=20mH R=0.05ohm Figure 11. DC fault current characteristics (a) with variable limiting inductance; (b) with variable Figure 11. DC fault current characteristics (a) with variable limiting inductance; (b) with R=0.05oh variable m L=20mH R=0.05ohm L=20mH 5 R=0.5ohm L=20mH R=0.05ohm L=100mH 4 energy dissipation resistance. energy dissipation resistance. x 10 R=5ohm L=20mH 4 4 R=0.05ohm L=200mH Table 4 2. Condition classiﬁcation for the fault current limiting circuit scheme. x 10 2 1 1.2 1.205 20000 1 Time Point Label Fault Occurred Fault Detected IGBT Blocked ad 0 ag 0 0 1.2 1.205 ae a X X Fault occurrence Fault occurrence bg af -1 Resistance-related -1 1.1 1.2 1.3 1.4 1.5 1.6 1.7 b X 1 1.1 ag 1.2 1.3 1.4 1.5 1.6 1.7 1.8 cg Time(s) condition ah Time(s) 5000 (a) ( d X X b) e X X Reactor-related Figure 11. 0 DC fault current characteristics (a) with variable limiting inductance; (b) with variable f X Fault 0 Fault condition Fault Fault occurrence IGBT blocked energy dissipation resi detected stance. IGBT blocked g oc currence detected -5000 -1000 1.199 1.2 1.201 1.202 1.203 1.204 1.205 1.199 1.2 1.201 1.202 1.203 1.204 1.205 h X X X Time(s) Time(s) (a) (b) ad ag ae Figure 12. Comparison among different FCL schemes (a) different resistance conditions without bg af ag considering the reactor, cg (b) different reactor conditions with selected resistance schemes. 3000 ah 5000 Table 2. Condition classification for the fault current limiting circuit scheme. Fault Fault IGBT Fault Fault 0 Time Point Label Fault Fault occurrence detected IGBT blocked Occurred Detected Blocke IGd BT blocked occurrence detected -5000 -1000 1.199 1.2 1.201 1.202 1.203 1.204 1.205 1.199 1.2 1.201 1.202 1.203 1.204 1.205 a ×   Resistance- Time(s) Time(s) related b ×  × (a) (b) condition c × × × Figure 12. Figure 12. Compari Comparison son among d d among di ifferent FCL erent FCL sschemes chemes (( aa) different res ) di er ent resistance istance cond conditions × iti ons withou without t consid considering ering the reactor, the reactor, ((b b)) d di ifferent reactor erent reactor conditions conditions wit with h sele selected cted resi resistance stance s schemes. chemes. e ×   Reactor- related f ×  × Table 2. Condition classification for the fault current limiting circuit scheme. condition g × × × h    Fault Fault IGBT Time Point Label Occurred Detected Blocked Resistance- a ×   related b ×  × condition c × × × d   × Reactor- e ×   related f ×  × condition g × × × h    DC Current(A) DC Current(A) DC Current(A) DC Current(A) DC Current(A) DC Current(A) DC Current(A) DC Current(A) Appl. Sci. 2019, 9, x 14 of 26 A series of simulations was conducted under controlled conditions to obtain the expected fault current limitation and rapid recovery. The simulation conditions are divided into resistance and reactor groups as follows: the former is labeled with “a”, “b”, “c”, and “d”, and the latter with “e”, “f”, “g”, and “h”. Specifically, the related explanations of the conditions are listed in Table 2. “” indicates that the resistance or reactor is inserted in the fault circuit, and “×” denotes the absence of Appl. Sci. 2019, 9, 1661 14 of 26 resistance or reactor. First, the reactor was ignored, and Figure 12a illustrates that the red curve (“ag”) provides an improved performance in limiting fault current. Thus, the condition with “a” was selected for the following simulation. Figure 12b depicts the performance of various reactor-based 3.2. Basic Topology FCLC scheme, in which the red dashed–dotted curve (“ad”) represents the lowest fault current level. The EFCLC is proposed on the basis of analyzing the fault current limitation characteristics However, the “ad” scheme was unsatisfactory for real projects, where large inductance will affect the (Figure 13). During the normal state, the series-connected IGBTs, namely, T and T , are opened. When 1 2 dynamic response speed of the entire system during the normal state. Therefore, the “af” scheme a fault is detected, T and T are closed by a switching-o signal, and the energy dissipation resistance 1 2 most closely approaches the optimized FCLC scheme, because the energy dissipation resistance R and FCL reactor L are inserted in the fault circuit. L will be bypassed via bidirectional FCL FCL FCL consumes the energy in the fault circuit. This phenomenon is due to the fault being detected, and the parallel-connected thyristors T and T . The surge arrestor is equipped to protect circuit components 3 4 FCL reactor being inserted to limit the increase in current speed, but also being removed to accelerate from surge current and voltage. In addition, the thyristors can function as a voltage stabilizer due to the decaying speed of the freewheeling current after blocking the IGBT. the surge voltage across L . Considering zero voltage switching and loss reduction, the IGBTs are FCL protected by a snubber circuit, which consists of snubber capacitor, snubber resistance, and diode [34]. 3.2. Basic Topology D D 1 2 T T 1 2 FCL R T FCL 3 MOA Figure 13. Proposed enhanced fault current limiting circuit. Figure 13. Proposed enhanced fault current limiting circuit. 3.3. Fault Current Interruption with DC Circuit Breaker The EFCLC is proposed on the basis of analyzing the fault current limitation characteristics (Figure 13). During the normal state, the series-connected IGBTs, namely, 𝑇 and 𝑇 , are opened. Considering that fault relay involves FCL behavior and DCCB operation, it is necessary to When a fault is detected, 𝑇 and 𝑇 are closed by a switching-off signal, and the energy dissipation investigate the coordination between EFCLC behavior and DCCB operation in this paper. Hence, resistance 𝑅 and FCL reactor 𝐿 are inserted in the fault circuit. 𝐿 will be bypassed via the fault interruption progress could be determined for further parameter setting of EFCLC. The bidirectional parallel-connected thyristors 𝑇 and 𝑇 . The surge arrestor is equipped to protect DCCB topologies in articles and patents can be classiﬁed into passive and active resonance DCCB, circuit components from surge current and voltage. In addition, the thyristors can function as a hybrid DCCB (HCB), and solid-state DCCB (SCB) [39]. The resonance-based DCCB spend a relatively voltage stabilizer due to the surge voltage across 𝐿 . Considering zero voltage switching and loss long time in fault current interruption and may lead to overcurrent. The HCB and SCB have a rapid reduction, the IGBTs are protected by a snubber circuit, which consists of snubber capacitor, snubber operation speed. Although the detailed topologies of the HCB and SCB are dierent from the nominal resistance, and diode [34]. path, these topologies can be equivalent to the ideal breaker in the nominal path and a metal oxide arrestor (MOA) when proactive switching control is applied [14,24]. A residential current breaker is 3.3 Fault Current Interruption with DC Circuit Breaker used to cut a residential current in the MOA, which is also modeled as an ideal breaker. The topologies of the DCCB and equivalent simulation model [14] are exhibited in Figure 14a,b, correspondingly. The Considering that fault relay involves FCL behavior and DCCB operation, it is necessary to main breaker demonstrated in Figure 14b will wait for the operation delay in ultrafast disconnector investigate the coordination between EFCLC behavior and DCCB operation in this paper. Hence, the switch (Figure 14a) operation, and the delay time is normally 2ms [33]. The fault current with a hybrid fault interruption progress could be determined for further parameter setting of EFCLC. The DCCB DCCB operation is exhibited in Figure 15. topologies in articles and patents can be classified into passive and active resonance DCCB, hybrid Figure 16 displays the fault current interruption sequence of the EFCLC with DCCB. T and T 1 2 DCCB (HCB), and solid-state DCCB (SCB) [39]. The resonance-based DCCB spend a relatively long are opened during the normal state, whereas T , T , and the DCCB main breaker are closed. When 3 4 time in fault current interruption and may lead to overcurrent. The HCB and SCB have a rapid a fault occurs, T and T remain open before a fault is detected, and the main breaker of the DCCB 1 2 operation speed. Although the detailed topologies of the HCB and SCB are different from the nominal remains closed (Figure 16a). When a fault is detected, T and T are switched o to insert an FCL 1 2 path, these topologies can be equivalent to the ideal breaker in the nominal path and a metal oxide branch in the fault circuit loop, and the DCCB main breaker remains closed due to operation time arrestor (MOA) when proactive switching control is applied [14,24]. A residential current breaker is delay [33] (Figure 16b). Thus, the fault current level and accelerating speed are limited by the FCL used to cut a residential current in the MOA, which is also modeled as an ideal breaker. The branch, which releases the overcurrent pressure on the IGBTs and diodes in the converter and reduces the requirement of the DCCB in an interruption capacity. Once the converter is blocked under an overcurrent protection, T and T are switched on to bypass L , and the DCCB main breaker is 3 4 FCL opened (Figure 16c). Consequently, R shares the fault current with the MOA in the DCCB, and the FCL fault circuit inductance is reduced to quickly extinguish the fault current. Afterward, when the current Appl. Sci. 2019, 9, x 15 of 26 Appl. Sci. 2019, 9, x 15 of 26 topologies of the DCCB and equivalent simulation model [14] are exhibited in Figure 14a and Figure topologies of the DCCB and equivalent simulation model [14] are exhibited in Figure 14a and Figure Appl. Sci. 2019, 9, 1661 15 of 26 14b, correspondingly. The main breaker demonstrated in Figure 14b will wait for the operation delay 14b, correspondingly. The main breaker demonstrated in Figure 14b will wait for the operation delay in ultrafast disconnector switch (Figure 14a) operation, and the delay time is normally 2ms [33]. The in ultrafast disconnector switch (Figure 14a) operation, and the delay time is normally 2ms [33]. The fault current with a hybrid DCCB operation is exhibited in Figure 15. level slightly decreases, the fault current will be cut via the residential current breaker. In addition, T , fault current with a hybrid DCCB operation is exhibited in Figure 15. T , T , and T are switched to their normal states. 2 3 4 MOA MOA (a) (b) (a) (b) Figure 14. (a) Direct current circuit breaker topology, (b) simplified simulation model. Figure 14. (a) Direct current circuit breaker topology, (b) simplified simulation model. Figure 14. (a) Direct current circuit breaker topology, (b) simpliﬁed simulation model. max max I Fault current B _max I Fault current without DCCB B _max without DCCB Fault current Fault current with DCCB with DCCB Fault current Fault current through arrestor through arrestor A. Fault occurs A. Fault occurs B. Fault detected B B. Fault detected C. Main breaker opens C. Main breaker opens D D. Residential current breaker opens D. Residential current breaker opens dN dN t t Bo _ p max ft t t max ft Bo _ p Appl. Sci. 2019, 9, x 16 of 26 Figure 15. Fault current with hybrid DCCB operation. Figure 15. Fault current with hybrid DCCB operation. Figure 15. Fault current with hybrid DCCB operation. D D D D 1 2 i i 1 2 fault fault Figure 16 displays the fault current interruption sequence of the EFCLC with DCCB. 𝑇 and 𝑇 Figure 16 displays the fault current interruption sequence of the EFCLC with DCCB. T T 𝑇 and 𝑇 T T 1 2 are opened during the normal state, whereas 𝑇 , 𝑇 , and the DCCB main breaker are closed. When a FCL are opened during the normal state, whereas 𝑇 , 𝑇 , and the DCCB main breaker are closed. When a R T L R T FCL 3 FCL MOA FCL 3 fault occurs, 𝑇 and 𝑇 remain open befo MOAre a fault is detected, and the main breaker of the DCCB fault occurs, 𝑇 and 𝑇 remain open before a fault is detected, and the main breaker of the DCCB remains closed (Figure 16a). Wh 4 en a fault is detected, 𝑇 and 𝑇 are switched off to insert an FCL remains closed (Figure 16a). When a fault is detected, 𝑇 and 𝑇 are switched off to insert an FCL MOA branch in the fault circui MOA t loop, and the DCCB main breaker remains closed due to operation time branch in the fault circuit loop, and the DCCB main breaker remains closed due to operation time delay [33] (Figure 16b). Thus, the fault current level and accelerating speed are limited by the FCL (a) (b) delay [33] (Figure 16b). Thus, the fault current level and accelerating speed are limited by the FCL D D branch, which releases the overcurrent pressure on the IGBTs and diodes in the converter and 1 2 D D i 1 2 fault branch, which releases the overcurrent pressure on the IGBTs and diodes in the conve fault rter and T T T 1 2 T reduces the requirement of the DCCB in an interruption capacity. O 1 nce the conve 2 rter is blocked under reduces the requirement of the DCCB in an interruption capacity. Once the converter is blocked under L L FCL FCL an overcurrent protection, 𝑇 and 𝑇 are switched on to bypass 𝐿 , and the DCCB main breaker R T R T FCL 3 FCL 3 MOA MOA an overcurrent protection, 𝑇 and 𝑇 are switched on to bypass 𝐿 , and the DCCB main breaker is opened (Figure 16c). Consequently, 𝑅 shares the fault current with the MOA in the DCCB, and T T is opened (Figure 16c). Consequently 4 , 𝑅 shares the fault current with the MOA in the DCCB, and the fault circuit inductance is reduced to quickly extinguish the fault current. Afterward, when the MOA MOA the fault circuit inductance is reduced to quickly extinguish the fault current. Afterward, when the current level slightly decreases, the fault current will be cut via the residential current breaker. In current level slightly decreases, the fault current will be cut via the residential current breaker. In (c) (d) addition,𝑇 ,𝑇 ,𝑇 , and 𝑇 are switched to their normal states. addition,𝑇 ,𝑇 ,𝑇 , and 𝑇 are switched to their normal states. Figure 16. Sequence of fault interruption. (a) After fault occurrence and before fault detection, (b) 𝑇 Figure 16. Sequence of fault interruption. (a) After fault occurrence and before fault detection, (b) T and and T𝑇 ar are swit e switched ched off o, (c , ( ) c DCCB ) DCCB operates, operates, T and 𝑇 and T ar 𝑇 e turned are turned on, ( on, (d) RCB d) RCB opens, opens, an and T and d 𝑇 T and are 2 3 4 3 4 turned 𝑇 are turned off o. . 4. Design of the Enhanced Fault Current Limiting Circuit 4.1. Design Objective The EFCLC aims to reduce the requirement for the interruption capacity and isolation speed in the DCCB. Several factors are considered to achieve the design objective. 1. The peak value of the DC line current 𝑖 must be limited under the maximum breaking current of the DCCB 𝐼 when the main breaker opens. 2. The fault current rising speed (𝑑𝑖 ⁄𝑑𝑡 ) must be lower than the largest rate of the current change withstood by the DCCB ((𝑑𝑖 𝑑𝑡 ) ). 3. In accordance with the fault current through the converter arms displayed in Figure 10, the freewheeling diodes still withstand overcurrent after blocking IGBTs. Thus, the DCCB is required to operate before the fault current reaches its maximum value. That is, the main breaker must open before the IGBT is blocked, thereby benefiting the system recovery and restart. The time period from fault occurrence to the DCCB operation (𝑡 ) must be shorter than the time consumed from fault occurrence to blocking IGBTs ( 𝑡 ). Specifically, 𝑡 involves the fault detection time (𝑡 ) and DCCB operation time (𝑡 ) (Figure 15). In accordance with the aforementioned points, the following condition can be obtained: max(iI ) < (38) dc B _max max(di / dt)(/ < di dt) (39) dc B _max tt>=t +t (40) bl op fd B _ op 4.2. Determination of Boundary Condition Reference [33] mentioned that the hybrid DCCB has been tested to interrupt the maximum fault current of 9 kA within 2 ms. Thus, 𝐼 is set to 9 kA in this study. The DCCB operation time 𝑡 _ _ is set to 2 ms. Therefore, (𝑑𝑖 𝑑𝑡 ⁄ ) is set to 9 kA/2 ms = 4.5 kA/ms. The fault detection time under the DC fault in the HVDC system has been reduced to within 1ms via a wavelet-based algorithm without using communication [40]. Consequently, the fault detection time 𝑡 can only be set to 1ms, and the capacitor discharging time 𝑡 must be more than 1 ms+2 ms =3 ms. The worst fault scenario has been adopted in this part as the PPF at the end of the DC overhead line. Furthermore, the threshold value of the arm current (𝐼 ) is normally set to twice as that of the rated current (𝐼 ) to block the IGBT. Therefore, I =2 × I = 2 × 1000A = 2000A with 𝐼 is set to 1000 A in this study. Appl. Sci. 2019, 9, 1661 16 of 26 4. Design of the Enhanced Fault Current Limiting Circuit 4.1. Design Objective The EFCLC aims to reduce the requirement for the interruption capacity and isolation speed in the DCCB. Several factors are considered to achieve the design objective. 1. The peak value of the DC line current i must be limited under the maximum breaking current dc of the DCCB I when the main breaker opens. B_max 2. The fault current rising speed (di /dt) must be lower than the largest rate of the current change dc withstood by the DCCB ((di/dt) ). B_max 3. In accordance with the fault current through the converter arms displayed in Figure 10, the freewheeling diodes still withstand overcurrent after blocking IGBTs. Thus, the DCCB is required to operate before the fault current reaches its maximum value. That is, the main breaker must open before the IGBT is blocked, thereby beneﬁting the system recovery and restart. The time period from fault occurrence to the DCCB operation (t ) must be shorter than the time consumed op from fault occurrence to blocking IGBTs (t ). Speciﬁcally, t involves the fault detection time op bl t and DCCB operation time t (Figure 15). In accordance with the aforementioned points, B_op f d the following condition can be obtained: max(i ) < I (38) dc B_max max(di /dt) < (di/dt) (39) dc B_max t > t = t + t (40) op bl f d B_op 4.2. Determination of Boundary Condition Reference [33] mentioned that the hybrid DCCB has been tested to interrupt the maximum fault current of 9 kA within 2 ms. Thus, I is set to 9 kA in this study. The DCCB operation time t is B_max B_op set to 2 ms. Therefore, (di/dt) is set to 9 kA/2 ms = 4.5 kA/ms. The fault detection time under B_max the DC fault in the HVDC system has been reduced to within 1 ms via a wavelet-based algorithm without using communication [40]. Consequently, the fault detection time t can only be set to 1ms, f d and the capacitor discharging time t must be more than 1 ms + 2 ms = 3 ms. The worst fault scenario bl has been adopted in this part as the PPF at the end of the DC overhead line. Furthermore, the threshold value of the arm current (I ) is normally set to twice as that of the rated current (I ) to block the IGBT. th Therefore, I = 2 I = 2 1000 A = 2000 A with I is set to 1000 A in this study. th N N The capacitor discharging current is deﬁned in Equation (9) on the basis of the fault current analysis discussed in Section 2. The contributions from the AC grid and distributed line capacitance are omitted here. According to Constraint (38), the time during fault detection and main breaker operation delay is 3 ms. max(i ) = i (t) < I = 9 kA (41) dc dis B_max t=3 ms The change rate in the DC fault current can be obtained using Equation (42); the change rate must be less than 4.5 kA/ms. max(di /dt) = max(i (t) ) < 4.5kA/ms (42) dc dis In reference to Equations (35) and (36), Constraint (40) must be considered to decrease the arm current at 3 ms less than the threshold value of blocking the IGBT after fault occurrence. i (t) < I = 2kA (43) arm th t=3ms Equations (35)–(37) express that the equivalent capacitance and inductance determine the fault current development and capacitor discharging time. Moreover, the fault current curve must be Appl. Sci. 2019, 9, 1661 17 of 26 separated into two stages using the proposed EFCLC (Figure 12b). Speciﬁcally, the fault current rising speed is higher in the ﬁrst 1 ms stage than in the rest time. Thus, the fault current change rate within the ﬁrst 1 ms must be limited by Constraint (42). Furthermore, the fault current value at 3 ms after fault occurrence must be obtained by superposing the fault current calculation in two discharging stages. Therefore, varying the fault circuit parameters, which are similarly considered in determining the capacitor discharging time, must be addressed. 4.3. Parametric Design Before the EFCLC is inserted in the fault circuit loop, the fault current is only limited via the smoothing reactor, which decides the maximum increase in the fault current rate. The minimum smoothing reactor can be obtained using Equation (9) considering the limitations in the DCCB withstanding fault current change rate (4.5 kA). The theoretical minimum smoothing reactor is 41.2 mH. However, the simulation result provides 43 mH with 4.2% error. The reason may be attributed to the consideration of DC line current under the normal states. The smoothing reactor L is set to 50 mH dc considering the margin. The EFCLC will be inserted to limit fault current rising speed and amplitude after detecting a fault. Thus, the fault current rising speed is less than the fault detection time; thus, Constraint (39) is satisﬁed by properly selecting a smoothing reactor. An initial test with the EFCLC has been performed. The energy dissipation resistance R is set FCL to 50 W, and the FCL reactor L is set to 100 mH. The simulation conditions “af” and “ah,” as listed FCL in Table 2, are compared here. The red dashed line in Figure 17 indicates that a fault occurs at 1.2 s and takes 1 ms to detect fault [37]. Furthermore, the delay in the IGBT of the EFCLC is disregarded here. The fault current change rate during Dt is approximately 4 kA/ms, which is expectedly limited under the maximum current change rate of the hybrid DCCB. The EFCLC is inserted in the fault current circuit at 1.201 s, and the fault current experiences a sharp decrease DI because a part of the electrical energy is stored in L . The fault current rising speed is lower during Dt than during Dt . FCL 2 1 Therefore, the fault current at 1.203 s (the main breaker opens) is limited to approximately 6.6 kA, which is far below the maximum breaking current of the DCCB. Moreover, L is bypassed by the FCL thyristor while the main breaker opens, and the fault current extinguishment can be accelerated. The initial simulation result suggests that Constraint (41) leads to the minimum value of L and R . FCL FCL Therefore, the controlled match of L and R must be investigated. The fault current at 1.201 s is FCL FCL consistently 4 kA given the unchanged fault circuit parameter. Therefore, Figure 17 presents that 4kA DI + DI < 9kA (44) 1 2 In comparison with the blue dashed-dotted line illustrated in Figure 17, two current curves share nearly the same part during Dt . Thus, DI can be obtained with a dierence between the current values 2 1 of the two discharging conditions. In accordance with Equation (9), DI is expressed as Equation (45). DI = i (t) i (t) (45) 1 dis_a f dis_ah t=1ms t=1ms Moreover, Equations (44) and (38) can be simpliﬁed as Equation (46), because the two current curves depicted in Figure 17 have nearly the same value at 1.203 s. i (t) < 9kA (46) dis_ah t=3ms The equivalent resistance R and equivalent inductance L are acquired as Equations (47) eq_ah eq_ah and (48), respectively. Thus, on the basis of Equation (9), the fault current i at 1.203 s can be dis_ah calculated. If R = 20 W, then L must be larger than 46.4 mH to limit the fault current at 1.203 s FCL FCL under 9 kA. The minimum L matched with R = 20 W has been veriﬁed via a controlled simulation FCL FCL (Figure 18). The simulation results of the EFCLC with controlled R and dierent L are compared FCL FCL (Figure 18). The fault current with the EFCLC (calculated L = 46.4 mH with R = 20 W) FCL_min FCL_min Appl. Sci. 2019, 9, x 18 of 26 values of the two discharging conditions. In accordance with Equation (9), ∆𝐼 is expressed as Equation (45). Δ=Ii ()t −i (t) (45) 1_ dis af dis_ ah tm== 11 s t ms Moreover, Equations (44) and (38) can be simplified as Equation (46), because the two current curves depicted in Figure 17 have nearly the same value at 1.203 s. it () < 9kA (46) dis _ ah tm =3 s The equivalent resistance 𝑅 and equivalent inductance 𝐿 are acquired as Equations _ _ (47) and (48), respectively. Thus, on the basis of Equation (9), the fault current 𝑖 at 1.203 s can be calculated. If 𝑅 =20 𝛺 , then 𝐿 must be larger than 46.4mH to limit the fault current at 1.203 s under 9 kA. The minimum 𝐿 matched with 𝑅 =20 𝛺 has been verified via a controlled simulation (Figure 18). The simulation results of the EFCLC with controlled 𝑅 and different 𝐿 are compared (Figure 18). The fault current with the EFCLC (calculated 𝐿 = 46.4 with 𝑅 =20 𝛺 ) reaches 9106 A at 1.203 s. Thus, the error rate of the theoretical calculation is Appl. Sci. 2019, 9, 1661 18 of 26 approximately 1.2% within a reasonable range, and the minimum 𝐿 can be set to 47mH. Constraint (43) can be analyzed using the arm current Equations (24) and (25) in Section 2. Setting reaches 9106 A at 1.203 s. Thus, the error rate of the theoretical calculation is approximately 1.2% within 𝑅 =20 𝛺 , the 𝐿 is calculated as 219mH to satisfy Constraint (43). The arm currents are a reasonable range, and the minimum L can be set to 47mH. Constraint (43) can be analyzed using compared under the calculated 𝐿 FCL and 𝐿 obtained via a simulation (Table 3). The _ _ the arm current Equations (24) and (25) in Section 2. Setting R = 20 W, the L is calculated FCL FCL_min calculated 𝐿 leads to the maximum arm current (2023.5 A), which can contribute to blocking as 219 mH to satisfy Constraint (43). The arm currents are compared under the calculated L the IGBTs. The error in the calculation method may be attributed to the circulating current FCL among _min and L obtained via a simulation (Table 3). The calculated L leads to the maximum arm FCL_min FCL_min arms. However, the simulation method provides expected results; that is, the currents of the six arms current (2023.5 A), which can contribute to blocking the IGBTs. The error in the calculation method are all limited under 2 kA at 1.203 s. Therefore, in the overall view of constrains, 𝐿 is may be attributed to the circulating current among arms. However, the simulation method provides approximately 225 mH when 𝑅 is set to 20 Ω. However, 𝐿 is selected as 250 mH with expected results; that is, the currents of the six arms are all limited under 2 kA at 1.203 s. Therefore, in 𝑅 =20 𝛺 considering the margin in the parameter setting. the overall view of constrains, L is approximately 225 mH when R is set to 20 W. However, FCL_min FCL L is selected as 250 mH with R = 20 W considering the margin in the parameter setting. FCL_min FCL RR=+ 2R +R eq _ ah fault dc FCL (47) R = R + 2R + R (47) eq_ah f ault dc FCL L =+LL 2 +L (48) eq_0 ah dc FCL L = L + 2L + L (48) eq_ah dc FCL Main breaker opens af ah EFCLC is inserted ΔI ΔI Fault occur Δt Δt 1.199 1.2 1.201 1.202 1.203 1.204 Ti Ti m m e( es /) s Appl. Sci. 2019, 9, x 19 of 26 Figure Figure 17. 17. Simulation Simulation resu results lts of of the DC the DC line line curr current with the EFCLC. ent with the EFCLC. L=43.6mH L=44mH L=45mH 9,106 L=46mH L=47mH 9,050 8,950 1.2029 1.203 1.203 1.203 -2000 1.199 1.2 1.201 1.202 1.203 1.204 Tim Time e/s (s) Figure Figure 18. 18. Simulation Simulation resu results lts of of the the contr controlle olled d R 𝑅 and and didiffere erentnt L 𝐿 . . FCL FCL Table 3. Arm currents under the calculated and simulated 𝐿 . 𝑳 = 𝟐𝟏𝟗 𝒎𝑯, 𝑹 = 𝟐𝟎 𝛀 𝑳 = 𝟐𝟐𝟓 𝒎𝑯, 𝑹 = 𝟐𝟎 𝛀 𝑳𝑭𝑪 𝑳𝑭𝑪 𝑳𝑭𝑪 𝑳𝑭𝑪 Phase-A upper arm current 1712.7 A Phase-A upper arm current 1668.3 A Phase-A lower arm current 2023.4 A Phase-A lower arm current 1999.2 A Phase-B upper arm current 2023.5 A Phase-B upper arm current 1999.1 A Phase-B lower arm current 1704.4 A Phase-B lower arm current 1680.2 A Phase-C upper arm current 1876.5 A Phase-C upper arm current 1834.3 A Phase-C lower arm current 1858.7 A Phase-C lower arm current 1852.3 A 5. Discussion Several existing FCL schemes were compared in terms of FCL ability, cost, power loss, and influence on recovery and restart operations. The energy dissipation resistance-based FCL method in Reference [14], the inductance-based FCL scheme [15,35], and the proposed EFCLC were simulated under controlled conditions in this section. 5.1. Fault Current-Limiting Ability Comparison To investigate the FCL ability, the bias voltage adopted in the scheme presented in Reference [15] is omitted for convenience, and the values of the FCL reactor and energy dissipation resistance are maintained in comparison with the FCL ability (𝑅 = 20 𝛺 , 𝐿 = 250 𝑚𝐻 ). In accordance with the FCL method in Reference [21], the AC feeding current can be limited via a parallel-connected thyristor, and the FCL ability is compared on the basis of the capacitor discharging current in the present study. Therefore, the AC feeding current is eliminated by switching off the start connector in the simulation while the DCCB operates. The simulation results of the arm and DC line currents with different FCL schemes are compared, as exhibited in Figure 19. The arm current with the resistance- based method (R-method) is limited to approximately 6 kA (Figure 19a). The arm currents with inductance-based method (I-method) and proposed scheme are restricted under 2 kA (Figure 19c and Figure 19e, respectively). The proposed method can accelerate the fault current decay while the main breaker opens. Thus, the freewheeling diodes and IGBTs can be protected from overcurrent for a long time, and the fault current isolation speed is shortened. The R-method has the worst FCL performance, thereby limiting the DC line current to approximately 18 kA (Figure 19b). By contrast, the I-method and the proposed method can restrain the DC line current under 5.5 kA (Figure 19d and Figure 19f, correspondingly). However, the DC line current with the I-method remains at a high level after the main breaker opens. In summary, the proposed scheme has an improved performance in limiting the fault current through converter arms and DC line. DC Current(A) DC current/A DC Current/A DC Current(A) 𝑚𝐻 Appl. Sci. 2019, 9, 1661 19 of 26 Table 3. Arm currents under the calculated and simulated L . FCL_min L = 219 mH, R = 20 W L = 225 mH, R = 20 W FCL FCL FCL FCL Phase-A upper arm current 1712.7 A Phase-A upper arm current 1668.3 A Phase-A lower arm current 2023.4 A Phase-A lower arm current 1999.2 A Phase-B upper arm current 2023.5 A Phase-B upper arm current 1999.1 A Phase-B lower arm current 1704.4 A Phase-B lower arm current 1680.2 A Phase-C upper arm current 1876.5 A Phase-C upper arm current 1834.3 A Phase-C lower arm current 1858.7 A Phase-C lower arm current 1852.3 A 5. Discussion Several existing FCL schemes were compared in terms of FCL ability, cost, power loss, and inﬂuence on recovery and restart operations. The energy dissipation resistance-based FCL method in Reference [14], the inductance-based FCL scheme [15,35], and the proposed EFCLC were simulated under controlled conditions in this section. 5.1. Fault Current-Limiting Ability Comparison To investigate the FCL ability, the bias voltage adopted in the scheme presented in Reference [15] is omitted for convenience, and the values of the FCL reactor and energy dissipation resistance are maintained in comparison with the FCL ability (R = 20 W, L = 250 mH). In accordance with the FCL FCL FCL method in Reference [21], the AC feeding current can be limited via a parallel-connected thyristor, and the FCL ability is compared on the basis of the capacitor discharging current in the present study. Therefore, the AC feeding current is eliminated by switching o the start connector in the simulation while the DCCB operates. The simulation results of the arm and DC line currents with dierent FCL schemes are compared, as exhibited in Figure 19. The arm current with the resistance-based method (R-method) is limited to approximately 6 kA (Figure 19a). The arm currents with inductance-based method (I-method) and proposed scheme are restricted under 2 kA (Figure 19c,e, respectively). The proposed method can accelerate the fault current decay while the main breaker opens. Thus, the freewheeling diodes and IGBTs can be protected from overcurrent for a long time, and the fault current isolation speed is shortened. The R-method has the worst FCL performance, thereby limiting the DC line current to approximately 18 kA (Figure 19b). By contrast, the I-method and the proposed method can restrain the DC line current under 5.5 kA (Figure 19d,f, correspondingly). However, the DC line current with the I-method remains at a high level after the main breaker opens. In summary, the proposed scheme has an improved performance in limiting the fault current through converter arms and DC line. 5.2. Cost The main cost of the proposed EFCLC lies in fault current-limiting inductance L , energy FCL dissipation resistance R , semiconductor switches, and surge arrester. Similar to the main breaker in FCL the hybrid DCCB, the number of IGBT depends on the voltage across the EFCLC. The amount and parameter selection of a surge arrester are also determined by protection requirement. The EFCLC can be regarded as an auxiliary circuit to share the energy absorption and electrical pressure by limiting the fault current under an acceptable level. Although IGBTs and surge arrester in EFCLC lead to extra cost, the HVDC system can ensure the fault interruption with a low risk on the DCCB failure. Moreover, according to the simulation result in Figure 19, the R-method adopted in References [14,41] has a higher fault current level than the proposed method during the fault interruption period, thereby indicating extra cost on interruption capacity, surge arrester, and the cooling system. Therefore, it might be economic to have EFCLC in protection operation, given its strength in FCL ability. Furthermore, lower peak fault current indicates less investment in DCCB interruption capability. The main expenditure of the I-method depends on the SFCL inductance technology because its unique characteristics can limit the fault current without aecting the system’s dynamic response speed. However, the immaturity of Appl. Sci. 2019, 9, 1661 20 of 26 the SFCL device leads to an increased cost to satisfy the protection requirement in terms of the system recovery and restart. Furthermore, compared with the proposed approach, the I-method requires additional cost in the energy dissipation component to accelerate the fault current extinguishment. In summary Appl. Sci. 2019 , taking , 9, x comprehensive consideration of economic eciency and FCL performance, EFCLC 20 of 26 deserves consideration to be applied in real project. 7000 20000 -1000 -5000 1.18 1.2 1.22 1.24 1.26 1.28 1.18 1.2 1.22 1.24 1.26 1.28 Time(s) Time(s) (a) (b) 2000 6000 -500 -1000 1.18 1.2 1.22 1.24 1.26 1.28 1.18 1.2 1.22 1.24 1.26 1.28 Time(s) Time(s) (c) (d) 2000 6000 -500 -1000 1.18 1.2 1.22 1.24 1.26 1.28 1.18 1.2 1.22 1.24 1.26 1.28 Time(s) Time(s) (e) (f) Figure 19. FCL ability comparison among existing methods: (a) Arm current in the resistance-based Figure 19. FCL ability comparison among existing methods: (a) Arm current in the resistance-based method, (b) DC line current in the resistance-based, (c) Arm current in the inductance-based method, method, (b) DC line current in the resistance-based, (c) Arm current in the inductance-based method, (d) DC line current in the inductance-based method, (e) Arm current in the proposed method, (f) DC (d) DC line current in the inductance-based method, (e) Arm current in the proposed method, (f) DC line current in the proposed method. line current in the proposed method. 5.3. Power Loss 5.2. Cost As explained in Section 4.3, the proposed scheme requires a smoothing reactor of 50 mH, thereby The main cost of the proposed EFCLC lies in fault current-limiting inductance 𝐿 , energy leading to power loss during the normal state. Considering that the resistance value of a 2 mH reactor dissipation resistance 𝑅 , semiconductor switches, and surge arrester. Similar to the main breaker equals 18.9 mW [42], the power loss P is expressed as Equation (49). in the hybrid DCCB, the number of IGBT depends on the voltage across the EFCLC. The amount and parameter selection of a surge arrester are also determined by protection requirement. The EFCLC 4I R L L r dN can be regarded as an auxiliary circuit to share the energy absorption and electrical pressure by P = 100% (49) cableN limiting the fault current under an acceptable level. Although IGBTs and surge arrester in EFCLC lead to extra cost, the HVDC system can ensure the fault interruption with a low risk on the DCCB failure. Moreover, according to the simulation result in Figure 19, the R-method adopted in References [14,41] has a higher fault current level than the proposed method during the fault interruption period, thereby indicating extra cost on interruption capacity, surge arrester, and the cooling system. Therefore, it might be economic to have EFCLC in protection operation, given its strength in FCL ability. Furthermore, lower peak fault current indicates less investment in DCCB Arm current(A) Arm current(A) Arm current(A) DC line current(A) DC line current(A) DC line current(A) Appl. Sci. 2019, 9, x 21 of 26 interruption capability. The main expenditure of the I-method depends on the SFCL inductance technology because its unique characteristics can limit the fault current without affecting the system’s dynamic response speed. However, the immaturity of the SFCL device leads to an increased cost to satisfy the protection requirement in terms of the system recovery and restart. Furthermore, compared with the proposed approach, the I-method requires additional cost in the energy dissipation component to accelerate the fault current extinguishment. In summary, taking comprehensive consideration of economic efficiency and FCL performance, EFCLC deserves consideration to be applied in real project. 5.3. Power Loss As explained in Section 4.3, the proposed scheme requires a smoothing reactor of 50 mH, thereby leading to power loss during the normal state. Considering that the resistance value of a 2 mH reactor equals 18.9 mΩ [42], the power loss 𝑃 is expressed as Equation (49). 4IR L dN L r P=×100% (49) Appl. Sci. 2019, 9, 1661 21 of 26 cableN where 𝐼 is the rated DC line current, 𝑅 = 0.00945 Ω/mH is based on Reference [43], 𝐿 is the where I is the rated DC line current, R = 0.00945 W/mH is based on Reference [43], L is the dN L r smoothing reactor, and 𝑃 is the rated DC line power. Thus, the smoothing reactor in the smoothing reactor, and P is the rated DC line power. Thus, the smoothing reactor in the proposed cablrN proposed scheme causes 0.135% power loss in comparison with the rated DC line power, thus scheme causes 0.135% power loss in comparison with the rated DC line power, thus denoting a denoting a promising economic efficiency. promising economic eciency. 5.4. Influence on Fault Current 5.4. Inﬂuence on Fault Current Figure 20a,b presents the influence of 𝑅 and 𝐿 on the DC line current, respectively. When Figure 20a,b presents the inﬂuence of R and L on the DC line current, respectively. When FCL FCL 𝑅 increases but 𝐿 remains at 250 mH, the DCCB capability requirement is low, and the fault R increases but L remains at 250 mH, the DCCB capability requirement is low, and the fault FCL FCL current extinguishment is accelerated (Figure 20a). When 𝐿 increases but 𝑅 remains at 20 Ω, current extinguishment is accelerated (Figure 20a). When L increases but R remains at 20 W, FCL FCL the peak value of the fault current decreases but the time spent in the fault current interruption is the peak value of the fault current decreases but the time spent in the fault current interruption is unaffected. Therefore, 𝐿 in the proposed scheme hardly influences the dynamic response or the unaected. Therefore, L in the proposed scheme hardly inﬂuences the dynamic response or the FCL fault current extinguishment. fault current extinguishment. 12000 12000 without EFCLC without EFCLC L =200mH FCL R =10Ω FCL L =300mH FCL R =20Ω FCL 8000 8000 L =400mH FCL R =50Ω FCL L =500mH FCL 6000 6000 R =100Ω FCL 4000 4000 2000 2000 0 0 1.2 1.205 1.21 1.215 1.22 1.225 1.23 1.235 1.2 1.205 1.21 1.215 1.22 1.225 1.23 1.235 Time(s) Time(s) (a) (b) Figure 20. DC line current with variables (a) 𝑅 and (b) 𝐿 . Figure 20. DC line current with variables (a) R and (b) L . FCL FCL 5.5. Inﬂuence on Energy Absorption 5.5. Influence on Energy Absorption Because of the isolation eect of the thyristor on the AC feeding current, the fault current during fault interruption is mainly the freewheeling current, given the energy stored in the smoothing reactor, whose path is depicted in Figure 21. The energy stored in the smoothing reactor can be obtained using Equation (50). E = 1/2L i (t ) (50) L dc op f ault where L is the smoothing reactor; i t is the fault current through the DC line while the DCCB dc f ault op operates, which can be obtained using Equation (9); and t is the time point of fault occurrences. t t op 0 C eq I ! dis0 0 i (t ) = e [U sin(! (t t )) sin(! (t t ) )] (51) op op op f ault dc 1 0 1 0 L ! eq 1 Appl. Sci. 2019, 9, x 22 of 26 D D 1 2 dc fault T T + 1 2 M − RCB FCL FCL 3 MOA + + − U − C 4 MOA Figure 21. Fault current path during fault interruption. Figure 21. Fault current path during fault interruption. Because of the isolation effect of the thyristor on the AC feeding current, the fault current during fault interruption is mainly the freewheeling current, given the energy stored in the smoothing reactor, whose path is depicted in Figure 21. The energy stored in the smoothing reactor can be obtained using Equation (50). E = 1/ 2Li (t ) (50) L dc fault op where 𝐿 is the smoothing reactor; 𝑖 (𝑡 ) is the fault current through the DC line while the DCCB operates, which can be obtained using Equation (9); and 𝑡 is the time point of fault occurrences. tt − op 0 − C I ω eq dis00 it ( )=− e [U sin(ωω (t t ))− sin( (t−t )−θ )] (51) fault op dc 10 op 1 op 0 L ω eq 1 The energy absorbed by 𝑅 can be expressed as EU== (/R )dtR(( i ) /R )dt (52) R R FCL FCL fault FCL  Then, the energy absorbed in the MOA of the DCCB can be expressed as E =−EE (53) M LR Figure 20b displays that a large smoothing reactor will lead to a small 𝑖 (𝑡 ). Thus, the energy stored in the smoothing reactor will decrease, thereby indicating a reduced energy consumed in the MOA and decreased time spent in the fault current interruption. Moreover, the fault detection time can influence the energy stored in the smoothing reactor in a positive relationship. Thus, determining the energy absorbed in 𝑅 must consider the effect of inductance and fault detection time to reduce stress on the MOA of the DCCB. The simulation result presented in Figure 22a shows that a large 𝑅 results in minimal energy absorption in the MOA of the DCCB given the low fault current level at the DCCB operation time point and shared energy absorption. Similarly, a large 𝐿 denotes a minimal energy absorbed in the MOA because an increase in 𝐿 leads to a low current and energy stored in 𝐿 when the main breaker opens. Overall, 𝑅 and 𝐿 can limit the fault current to a relatively low level to reduce the energy absorbed in the MOA of the DCCB. However, a balance between the DCCB and EFCLC is observed in terms of energy consumption during the fault current-limiting period and fault current extinguishment stage. Therefore, the tradeoff between FCL performance and additional cost on the snubber circuit and cooling system of the EFCLC must be considered. DC line current(A) DC line current(A) Appl. Sci. 2019, 9, 1661 22 of 26 The energy absorbed by R can be expressed as FCL Z Z E = (U /R )dt = ((R i ) /R )dt (52) FCL FCL f ault FCL Then, the energy absorbed in the MOA of the DCCB can be expressed as E = E E (53) M L R Figure 20b displays that a large smoothing reactor will lead to a small i t . Thus, the energy op f ault stored in the smoothing reactor will decrease, thereby indicating a reduced energy consumed in the MOA and decreased time spent in the fault current interruption. Moreover, the fault detection time can inﬂuence the energy stored in the smoothing reactor in a positive relationship. Thus, determining the energy absorbed in R must consider the eect of inductance and fault detection time to reduce FCL stress on the MOA of the DCCB. The simulation result presented in Figure 22a shows that a large R FCL results in minimal energy absorption in the MOA of the DCCB given the low fault current level at the DCCB operation time point and shared energy absorption. Similarly, a large L denotes a minimal FCL energy absorbed in the MOA because an increase in L leads to a low current and energy stored in FCL L when the main breaker opens. Overall, R and L can limit the fault current to a relatively low dc FCL FCL level to reduce the energy absorbed in the MOA of the DCCB. However, a balance between the DCCB and EFCLC is observed in terms of energy consumption during the fault current-limiting period and fault Appl. curr Sci. ent 2019extinguishment , 9, x stage. Therefore, the tradeo between FCL performance and additional 23 of 26 cost on the snubber circuit and cooling system of the EFCLC must be considered. x 10 4.5 L =500mH L =200mH FCL FCL 3.5 L =400mH L =300mH FCL FCL L =300mH L =400mH FCL FCL 2.5 L =200mH L =500mH FCL FCL 1.5 0.5 20 40 60 80 100 20 40 60 80 100 R (Ω) R (Ω) FCL FCL (a) (b) Figure 22. Characteristic curves of absorbed energy and interruption time under variables (a) 𝑅 Figure 22. Characteristic curves of absorbed energy and interruption time under variables (a) R and FCL and (b) 𝐿 . (b) L . FCL 5.6. Inﬂuence on Fault Interruption Time 5.6. Influence on Fault Interruption Time Although L is involved in the EFCLC, it can still be bypassed by the thyristor after the main FCL Although 𝐿 is involved in the EFCLC, it can still be bypassed by the thyristor after the main breaker operates. Thus, the fault current extinguishment speed cannot be delayed due to large breaker operates. Thus, the fault current extinguishment speed cannot be delayed due to large inductance. As mentioned in Section 5.5, the fault current level is restricted by a large R and FCL inductance. As mentioned in Section 5.5, the fault current level is restricted by a large 𝑅 and 𝐿 , L , and the interruption time can be reduced at a low fault current level at the beginning of fault FCL and the interruption time can be reduced at a low fault current level at the beginning of fault extinguishment. According to the expression of the attenuation coecient during the fault interruption extinguishment. According to the expression of the attenuation coefficient during the fault expressed in Equation (37), the large R can accelerate extinguishment speed. In summary, the FCL interruption expressed in Equation (37), the large 𝑅 can accelerate extinguishment speed. In interruption time is reduced when the values of R and L are high. This result agrees with the FCL FCL summary, the interruption time is reduced when the values of 𝑅 and 𝐿 are high. This result simulation result demonstrated in Figure 22b. agrees with the simulation result demonstrated in Figure 22b. 5.7. Practicality and Necessity of Proposed Circuit According to the study in this section, the proposed FCL circuit has better performance in limiting fault current under DC pole-to-pole fault, compared with previous FCL method under same parameter setting. In the viewpoint of reality, the power loss during normal state is considered acceptable as analyzed in section 5.3. In order to cooperate with protection relaying, the proposed FCL circuit is installed at the ends of transmission line so that communication delay among DCCB, measure point and protection relay could be reduced. Moreover, big smoothing reactor (200 mH) in [42–44] would influence the dynamic response speed and proposed FCL circuit could help reduce value of smoothing reactor for better performance of dynamic response. However, it requires further investigation on economic efficiency of proposed method, considering previous FCL methods, such as superconductor based fault current limiter, FCL circuit and converter topology based approach. Another point should be noted that the proposed EFCLC would make more contribution to fault interruption and clearance, compared with traditional FCL behavior with DC terminal reactor. The basic advantage of EFCLC over DC terminal reactor could be summarized as following aspects. Firstly, EFCLC is only triggered as fault detected to limit fault current, thereby having no influence on normal state and system dynamic response. By contrast, to achieve the same level of FCL performance of EFCLC, larger DC terminal reactor is required even under normal state, which does affect system dynamic response. Seconded, compared with DC terminal reactor, EFCLC could accelerate fault clearing speed due to its energy dissipation resistor. The last but not the least, the FCL inductor in EFCLC would be bypassed after IGBT blocks. Hence, the fault isolation time would be reduced to some degree since remained inductor would delay the fault current clearance. 5.8. Effectiveness of the Proposed Circuit E (J) t (ms) IN Appl. Sci. 2019, 9, 1661 23 of 26 5.7. Practicality and Necessity of Proposed Circuit According to the study in this section, the proposed FCL circuit has better performance in limiting fault current under DC pole-to-pole fault, compared with previous FCL method under same parameter setting. In the viewpoint of reality, the power loss during normal state is considered acceptable as analyzed in Section 5.3. In order to cooperate with protection relaying, the proposed FCL circuit is installed at the ends of transmission line so that communication delay among DCCB, measure point and protection relay could be reduced. Moreover, big smoothing reactor (200 mH) in [42–44] would inﬂuence the dynamic response speed and proposed FCL circuit could help reduce value of smoothing reactor for better performance of dynamic response. However, it requires further investigation on economic eciency of proposed method, considering previous FCL methods, such as superconductor based fault current limiter, FCL circuit and converter topology based approach. Another point should be noted that the proposed EFCLC would make more contribution to fault interruption and clearance, compared with traditional FCL behavior with DC terminal reactor. The basic advantage of EFCLC over DC terminal reactor could be summarized as following aspects. Firstly, EFCLC is only triggered as fault detected to limit fault current, thereby having no inﬂuence on normal state and system dynamic response. By contrast, to achieve the same level of FCL performance of EFCLC, larger DC terminal reactor is required even under normal state, which does aect system dynamic response. Seconded, compared with DC terminal reactor, EFCLC could accelerate fault clearing speed due to its energy dissipation resistor. The last but not the least, the FCL inductor in EFCLC would be bypassed after IGBT blocks. Hence, the fault isolation time would be reduced to some degree since remained inductor would delay the fault current clearance. 5.8. Eectiveness of the Proposed Circuit With application of the proposed EFCLC in fault loop, the requirement of DCCB’s interruption ability is reduced, and fault current interruption speed is accelerated. A comparison is performed in Table 4 between a fault situation with EFCLC and that without EFCLC, in terms of maximum fault current and fault interruption time. As mentioned in Section 4.3, L and R are set as 250 mH FCL_min FCL and 20 W in the test circuit. The test results shown in Table 3 reﬂect that the peak fault current needed to interrupt at DCCB operation is reduced from 12.4 kA to 5.1 kA with the help of EFCLC. Meanwhile, the time taken for the whole fault interruption process decreases from 34.8 ms to 13.6 ms. In summary, the eectiveness of the proposed circuit is veriﬁed, and reduced peak fault current and accelerated fault interruption would contribute to lower cost in relay and fast fault clearance. Table 4. Eectiveness veriﬁcation of enhance fault current limiting circuit. Term Requirement of Fault Current Interruption Fault Interruption Time Without EFCLC 12.4 kA 34.8 ms With EFCLC 5.1 kA 13.6 ms Improvement 41.1% 39.1% 6. Conclusions An EFCLC has been proposed and investigated in this study to reduce the DCCB requirement in terms of fault interruption capability and breaking speed. The EFCLC mainly consists of the energy dissipation resistor and FCL reactor. These devices are plugged into the fault loop after fault detection to limit the fault current rising speed and fault current level. Thus, while the DCCB operates, the fault current level is restrained, and the energy stored in the smoothing reactor is also reduced. Consequently, the fault current extinguishment stage can be accelerated given the increased energy dissipation resistor and decreased energy storage. Furthermore, the FCL reactor can be bypassed to accelerate the decaying of the freewheeling current. Moreover, the AC feeding current is eliminated via the bidirectional parallel-connected thyristor, whose feasibility and eectiveness have been veriﬁed in Appl. Sci. 2019, 9, 1661 24 of 26 existing works. Thus, this study focused on the methods for limiting fault current caused by capacitor discharging in the FCLC design. The proposed EFCLC has been veriﬁed to limit fault current under an expected level with a proper parameter setting on components. However, the performance tradeo and additional cost of the EFCLC must be considered in terms of the cooling system, surge arrester, and overvoltage protection. The development of the EFCLC in the multi-terminal HVDC system, the related fault protection scheme, and the FRT strategy will be investigated in future research. Author Contributions: All the authors have contributed to this paper in dierent aspects. Q.H. proposed the original concept and wrote the original draft. K.L. and L.Q. acted as supervisor and gave suggestions on paper improvement. S.Z., X.L. and Y.L. helped with software simulation and methodology improvement. Last but not least, H.D. contributed to paper editing and reviewing. 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Enhanced Fault Current-Limiting Circuit Design for a DC Fault in a Modular Multilevel Converter-Based High-Voltage Direct Current System

Enhanced Fault Current-Limiting Circuit Design for a DC Fault in a Modular Multilevel Converter-Based High-Voltage Direct Current System

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Enhanced Fault Current-Limiting Circuit Design for a DC Fault in a Modular Multilevel Converter-Based High-Voltage Direct Current System

Enhanced Fault Current-Limiting Circuit Design for a DC Fault in a Modular Multilevel Converter-Based High-Voltage Direct Current System

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