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A Novel Top-Down Fabrication Process for Vertically-Stacked Silicon-Nanowire Array

A Novel Top-Down Fabrication Process for Vertically-Stacked Silicon-Nanowire Array applied sciences Article A Novel Top-Down Fabrication Process for Vertically-Stacked Silicon-Nanowire Array Kangil Kim, Jae Keun Lee, Seung Ju Han and Sangmin Lee * Department of Biomedical Engineering, Kyung Hee University, Yongin 17104, Korea; kimkangil@khu.ac.kr (K.K.); wormsvkvk@khu.ac.kr (J.K.L.); sscandidate22@khu.ac.kr (S.J.H.) * Correspondence: sangmlee@khu.ac.kr; Tel./Fax: +82-31-201-2568 Received: 19 December 2019; Accepted: 4 February 2020; Published: 8 February 2020 Abstract: Silicon nanowires are widely used for sensing applications due to their outstanding mechanical, electrical, and optical properties. However, one of the major challenges involves introducing silicon-nanowire arrays to a specific layout location with reproducible and controllable dimensions. Indeed, for integration with microscale structures and circuits, a monolithic wafer-level process based on a top-down silicon-nanowire array fabrication method is essential. For sensors in various electromechanical and photoelectric applications, the need for silicon nanowires (as a functional building block) is increasing, and thus monolithic integration is highly required. In this paper, a novel top-down method for fabricating vertically-stacked silicon-nanowire arrays is presented. This method enables the fabrication of lateral silicon-nanowire arrays in a vertical direction, as well as the fabrication of an increased number of silicon nanowires on a finite dimension. The proposed fabrication method uses a number of processes: photolithography, deep reactive-ion etching, and wet oxidation. In applying the proposed method, a vertically-aligned silicon-nanowire array, in which a single layer consists of three vertical layers with 20 silicon nanowires, is fabricated and analyzed. The diamond-shaped cross-sectional dimension of a single silicon nanowire is approximately 300 nm in width and 20 m in length. The developed method is expected to result in highly-sensitive, reproducible, and low-cost silicon-nanowire sensors for various biomedical applications. Keywords: silicon nanowire; top-down fabrication; monolithic process; vertically-stacked array 1. Introduction Silicon nanowires are widely used for sensing applications due to their outstanding mechanical, electrical, and optical properties. Accordingly, research is currently being conducted on the physical properties of silicon nanowires, as well as on their manufacturing methods and applications [1–5]. Indeed, technology is being developed to use silicon nanowires as sensing elements, with further research being conducted in terms of possible integration with complementary metal-oxide-semiconductor (CMOS) circuits [6,7]. In the case of silicon nanowires, the physical and chemical properties are largely dependent on the surface-to-volume ratio and the quantum-size e ect, which are atypical compared with conventional macroscale materials [8]. Since the surface-to-volume ratio is enormous in the nanoscale dimension, sensing apparatuses that consist of nanostructures exhibit ultrasensitive properties for surface changes. This possibility has resulted in many methods of fabricating silicon nanowire-based biosensing platforms, all of which provide label-free and highly responsive sensing in real time [9–13]. Thus, a sensor platform with highly-sensitive silicon nanowires is a viable alternative; moreover, it can facilitate the combination of multiple functions within a single sensor using the same structure of silicon-nanowire building blocks [14]. Appl. Sci. 2020, 10, 1146; doi:10.3390/app10031146 www.mdpi.com/journal/applsci Appl. Sci. 2020, 10, 1146 2 of 10 The major challenge for sensor applications of silicon nanowires is to introduce silicon-nanowire arrays to a specific layout location with reproducible and controllable dimensions. However, the bottom-up fabrication method of silicon nanowires using the metallic-catalyst growth method has diculties with respect to the exact positioning of nanowires. In addition, due to the randomly oriented growth and inconsistent distribution of the required dimensions, the control of structural parameters is also an issue that needs to be resolved [15]. In addition, many researchers have reported nanostructure fabrication using metal-assisted chemical etching processes [16–18]. This is a method to fabricate nanostructures of vertically-aligned structures by patterning metal on the substrate. This makes it possible to fabricate well-aligned vertical nanostructures according to patterned metals, but for fabrication of laterally-aligned silicon-nanowire arrays, the aligned structures can be deformed during substrate transfer [19], or the separation of nanostructures from the substrate can be dicult [20]. The Si/SiGe epitaxy method has also been reported to fabricate the nanowire [21]. The epitaxial method allows for very tight control of the film thickness; however, the stacked epitaxial layers require careful control on the film stress to obtain reproducible electrical characteristics. Among the alternative fabrication approaches, the most promising technique is based on the top-down fabrication of silicon nanowires on a silicon-on-insulator (SOI) substrate. For sensors using silicon nanowires as a sensing structure, the sensor characteristics are determined according to the dimensions of the nanowires, which must to be controllable within the tunable range of electronics. In previous studies, a method of fabricating silicon nanowires by defining a pattern width by e-beam lithography (EBL) on an SOI wafer with a thin top layer has been reported [4]. In addition, silicon nanowires can be fabricated by defining microscale patterns using conventional ultraviolet (UV) lithography and then narrowing the pattern width through wet oxidation processes [5,6,22]. As a result of our previous work, we reported on the fabrication of silicon nanowires using (100)- and (111)-single crystalline silicon, as shown in Figure 1. The authors fabricated junctionless FETs and photodetectors using silicon nanowires fabricated from top-down methods. The results of the previously reported papers confirm that the number of silicon nanowires a ects the sensor characteristics rather than the morphology of individual nanowires [22]. The fabrication method developed herein is based on a number of processes: UV lithography, silicon dry-etching, anisotropic wet-etching, and thermal oxidation. The UV lithography has an advantage in terms of cost and wafer-level process rather than E-beam lithography. In addition, this process has advantages in terms of the substrate transfer process for manufacturing flexible electronic devices, as shown in our previous papers. The width of the silicon nanowire is defined according to the precisely-controlled wet-oxidation time. Figure 1 shows the fabrication of a laterally aligned silicon-nanowire array in a single layer. However, for sensors that use silicon-nanowire structures, both sensitivity and dynamic range depend on the number and dimension of silicon nanowires. Indeed, according to the aforementioned methods, increasing the number of silicon nanowires to improve overall performance inevitably increases the size of the device in question. In this paper, a novel top-down method for fabricating vertically-stacked silicon-nanowire array is presented. Compared to previous results, this method enables the fabrication of lateral silicon-nanowire arrays in a vertical direction, thereby enabling an increased number of silicon nanowires on a finite dimension, which, in turn, results in increased sensitivity and dynamic range. The proposed fabrication process uses a single UV lithography process, multiple deep reactive-ion etching (DRIE) processes, and a wet-oxidation process. The number and dimensions of the silicon nanowires are determined according to the DRIE-process conditions and the wet-oxidation process times; moreover, it is possible to fabricate multiple silicon nanowires at a single location by UV lithography. The remainder of this paper explains the detailed monolithic-fabrication process of vertically-stacked silicon-nanowire arrays. This is followed by a dimensional and structural analysis of the fabrication results in relation to the specific process steps. The manuscript concludes with a discussion on the implications of the method as well as the applicable areas. Appl. Sci. 2020, 10, x FOR PEER REVIEW 10 of 10 The remainder of this paper explains the detailed monolithic-fabrication process of vertically- stacked silicon-nanowire arrays. This is followed by a dimensional and structural analysis of the fabrication results in relation to the specific process steps. The manuscript concludes with a Appl. Sci. 2020, 10, 1146 3 of 10 discussion on the implications of the method as well as the applicable areas. (a) (b) Figure 1. Previously reported silicon-nanowire array fabricated by top-down processes. (a) (100) Figure 1. Previously reported silicon-nanowire array fabricated by top-down processes. (a) (100) silicon-nanowire array [5] (Reproduced with permission from Lee et al., Sensors and Materials; silicon-nanowire array [5] (Reproduced with permission from Lee et al., Sensors and Materials; published by MY K.K., 2012); (b) (111) silicon-nanowire array [6] (Reproduced with permission from published by MY K.K., 2012); (b) (111) silicon-nanowire array [6] (Reproduced with permission from Lee et al., Journal of Micromechanics and Microengineering; published by IOP Publishing 2014). Lee et al., Journal of Micromechanics and Microengineering; published by IOP Publishing 2014). 2. Fabrication Process 2. Fabrication Process The major challenge during the monolithic fabrication of a vertically-stacked silicon-nanowire The major challenge during the monolithic fabrication of a vertically-stacked silicon-nanowire array is the isolation between the layers of laterally-aligned silicon nanowires. To address this challenge, array is the isolation between the layers of laterally-aligned silicon nanowires. To address this the fabrication process proposed in this paper is based on the Bosch process [23], which is used to challenge, the fabrication process proposed in this paper is based on the Bosch process [23], which is fabricate anisotropic structures with high aspect ratios. In the Bosch process, by controlling the etching used to fabricate anisotropic structures with high aspect ratios. In the Bosch process, by controlling time for the isotropic-silicon etching step, it is possible to define the fabrication region of the silicon the etching time for the isotropic-silicon etching step, it is possible to define the fabrication region of nanowire as well as the region where the isolation layer is fabricated. By using the wet-oxidation the silicon nanowire as well as the region where the isolation layer is fabricated. By using the wet- process, which consumes silicon in order to produce silicon-dioxide (SiO ) and results in the insulation oxidation process, which consumes silicon in order to produce silicon-dioxide (SiO2) and results in layer, vertical isolation between the upper and lower layers is achieved. the insulation layer, vertical isolation between the upper and lower layers is achieved. Based on this concept, the top-down fabrication proposed in this paper is depicted in Figure 2. Based on this concept, the top-down fabrication proposed in this paper is depicted in Figure 2. As previously mentioned, it uses a combination of photolithography, DRIE, and a wet-oxidation As previously mentioned, it uses a combination of photolithography, DRIE, and a wet-oxidation process. Moreover, a p-type (111)-oriented single-crystalline silicon wafer is used, which has a diameter process. Moreover, a p-type (111)-oriented single-crystalline silicon wafer is used, which has a of 100 mm, a thickness of 525 m, and a resistivity of 1–10 Wcm. The reason for using (111)-silicon diameter of 100 mm, a thickness of 525 μm, and a resistivity of 1–10 Ω∙cm. The reason for using (111)- instead of the commonly used (100)-silicon is to allow the current to flow through the silicon nanowires silicon instead of the commonly used (100)-silicon is to allow the current to flow through the silicon rather than the bulk silicon part. In fact, (100)-silicon can also be used to fabricate laterally-aligned nanowires rather than the bulk silicon part. In fact, (100)-silicon can also be used to fabricate laterally- silicon-nanowire arrays, as our group has also reported in previous publication [5]. However, in the aligned silicon-nanowire arrays, as our group has also reported in previous publication [5]. However, case of (100)-silicon, only a single layer can be manufactured due to the orientation of the {111} plane in the case of (100)-silicon, only a single layer can be manufactured due to the orientation of the {111} and the wet etching characteristics of the silicon. In this paper, we need to implement a multiple plane and the wet etching characteristics of the silicon. In this paper, we need to implement a multiple layer-stacked array of silicon nanowires and isolate them from the silicon bulk. The (111) silicon is layer-stacked array of silicon nanowires and isolate them from the silicon bulk. The (111) silicon is suitable for isolating the nanowire from the substrate because the silicon is rapidly etched sideways suitable for isolating the nanowire from the substrate because the silicon is rapidly etched sideways during wet etching [6]. This facilitates the isolation of multilayered-nanowire array structures from during wet etching [6]. This facilitates the isolation of multilayered-nanowire array structures from the silicon bulk. First, as shown in Figure 2a, an oxide-mask layer (3000 Å thick) is deposited by a the silicon bulk. First, as shown in Figure 2a, an oxide-mask layer (3000 Å thick) is deposited by a plasma-enhanced chemical vapor deposition (PECVD) process, with a radio frequency (RF) power of plasma-enhanced chemical vapor deposition (PECVD) process, with a radio frequency (RF) power of 350 W, an O flow rate of 150 sccm, and a tetraethyl-orthosilicate (TEOS) flow rate of 150 sccm. The 350 W, an O2 flow rate of 150 sccm, and a tetraethyl-orthosilicate (TEOS) flow rate of 150 sccm. The TEOS layer is used as a passivation hard mask for bulk silicon etching. A GRX-601 (AZ Electronic TEOS layer is used as a passivation hard mask for bulk silicon etching. A GRX-601 (AZ Electronic Materials, Luxembourg) photoresist (PR) film is spin-coated on the TEOS layer with a rotation speed Materials, Luxembourg) photoresist (PR) film is spin-coated on the TEOS layer with a rotation speed of 4000 rpm and exposed to a UV light source with a wavelength of 365 nm for 3.1 s. Following the of 4000 rpm and exposed to a UV light source with a wavelength of 365 nm for 3.1 s. Following the exposure, the PR is developed in an AZ 300 MIF developer for 18 s and then rinsed in deionized (DI) water, as shown in Figure 2b. The photolithography step defines the in-plane dimension of the silicon-nanowire arrays, such as the pattern width and length. Appl. Sci. 2020, 10, x FOR PEER REVIEW 10 of 10 exposure, the PR is developed in an AZ 300 MIF developer for 18 s and then rinsed in deionized (DI) water, as shown in Figure 2b. The photolithography step defines the in-plane dimension of the silicon-nanowire arrays, such as the pattern width and length. After PR patterning, the TEOS hard-mask layer is etched by an inductive-coupled plasma (ICP) etcher with a CHF3 flow rate of 25 sccm, a CF4 flow rate of 5 sccm, and a pressure of 130 mTorr with an RF power of 600 W, as depicted in Figure 2c. The target etching thickness of the TEOS layer is calculated to be approximately 110% of the deposited thickness, which guarantees the exposure of the silicon surface. As shown in Figure 2d, after the PR strip step, a piranha solution (a mixture of sulfuric acid and hydrogen peroxide) cleaning process and an O2 plasma ashing process are conducted to remove the residuals. In Figure 2e, the bulk silicon is etched using a cyclic DRIE process, which consists of a single deposition step and two etching steps. In a conventional Bosch process, polymer deposition, polymer etching, and isotropic-silicon etching are conducted for five seconds, three seconds, and five seconds, respectively, in order to configure a high aspect-ratio structure. However, the process developed in this paper controls the final silicon etching time to fabricate the protrusion structures, which are in a location where the silicon nanowires are formed. The detailed DRIE process is summarized in Table 1. Several experiments are performed to optimize the adequate scallop size by tuning the duration of the isotropic-silicon etching step. As shown in Figure 2f, a thermal wet-oxidation process is conducted to define the width and thickness of the silicon nanowire, both of which can be precisely controlled according to the wet- oxidation time. The process is performed under a temperature of 1000 °C with an H2 flow rate of 7000 sccm and an O2 flow rate of 6500 sccm. In essence, the wet-oxidation process consumes silicon to produce thermal oxide; hence, the silicon nanowires are fabricated under a protrusion structure, while the vertical layers are isolated by the insulation layers. In this paper, Bosch 5/3/15 process is used for DRIE, and the purpose is to fabricate nanowires with a width of approximately 300 nm. The wet oxidation rate of the furnace used in this process is approximately 50 Å/min to form nanostructures, and the oxidation process is performed for about 70 min to isolate each layer by completely oxidizing the support structure. The additional oxidation is 20–25% more than the width of the support structure because the rate of oxidation is slower than the surface. After removing the TEOS and thermal oxide layers by hydrofluoric (HF)-acid dipping, the vertically-stacked silicon-nanowire arrays are formed. The number of vertical layers can be adjusted by the number of DRIE-process cycles without additional masking or photolithography processes. Appl. Sci. 2020, 10, 1146 4 of 10 Appl. Sci. 2020, 10, x FOR PEER REVIEW 10 of 10 (a) (b) (c) (d) (e) (f) Si SiO PR Wet Oxidation Figure 2. Fabrication process flow. (a) TEOS deposition; (b) PR patterning using UV lithography; (c) Figure 2. Fabrication process flow. (a) TEOS deposition; (b) PR patterning using UV lithography; (c) TEOS patterning; (d) PR removal; (e) DRIE for fabricating protrusion and support structure; (f) wet TEOS patterning; (d) PR removal; (e) DRIE for fabricating protrusion and support structure; (f) wet oxidation for nanowire fabrication and layer-to-layer isolation. oxidation for nanowire fabrication and layer-to-layer isolation. After PR patterning, the TEOS hard-mask layer is etched by an inductive-coupled plasma (ICP) Table 1. DRIE process steps for process development. etcher with a CHF flow rate of 25 sccm, a CF flow rate of 5 sccm, and a pressure of 130 mTorr with an 3 4 RF power of 600 W, as depicted in Figure 2c. The target etching thickness of the TEOS layer is calculated Gas Flow Coil Power Platen Power Pressure to be approximately 110% of the deposited thickness, which guarantees the (sccm exposur ) e of the silicon Time (s) (W) (W) (mTorr) surface. As shown in Figure 2d, after the PR strip step, a piranha solution (a mixture of sulfuric acid and C4F8 SF6 Ar hydrogen peroxide) cleaning process and an O plasma ashing process are conducted to remove the residuals. In Figure 2e, the bulk silicon is etched using a cyclic DRIE process, which consists of a single Polymer 825 1 22 100 0.5 30 5 deposition deposition step and two etching steps. In a conventional Bosch process, polymer deposition, polymer etching, and isotropic-silicon etching are conducted for five seconds, three seconds, and five seconds, Polymer etch 825 13 23 0.5 50 30 3 respectively, in order to configure a high aspect-ratio structure. However, the process developed in this paper controls the final silicon etching time to fabricate the protrusion structures, which 5, 7, 10 ar , 15 e in , a Silicon etch 825 13 23 0.5 100 30 location where the silicon nanowires are formed. The detailed DRIE process is summarized in Table 1. Several experiments are performed to optimize the adequate scallop size by tuning the duration of the isotropic-silicon etching step. 3. Fabrication Results As shown in Figure 2f, a thermal wet-oxidation process is conducted to define the width and For the fabrication of vertically-stacked silicon-nanowire arrays, it is necessary to define a thickness of the silicon nanowire, both of which can be precisely controlled according to the wet- structure with protrusion and support, as shown in Figure 3. Indeed, the d  ifference between the oxidation time. The process is performed under a temperature of 1000 C with an H flow rate of protrusion and support widths determines the wet-oxidation process time, which, in turn, 7000 sccm and an O flow rate of 6500 sccm. In essence, the wet-oxidation process consumes silicon determines the dimensions of the silicon nanowires fabricated in the protrusion. In addition, if the to produce thermal oxide; hence, the silicon nanowires are fabricated under a protrusion structure, width of the support is too narrow, or if the support does not form, then the thermal oxide layer will while the vertical layers are isolated by the insulation layers. In this paper, Bosch 5/3/15 process is used not grow uniformly during the wet-oxidation process. Therefore, the most critical step of the for DRIE, and the purpose is to fabricate nanowires with a width of approximately 300 nm. The wet proposed fabrication method is the DRIE process, especially the isotropic-silicon etching step, which oxidation rate of the furnace used in this process is approximately 50 Å/min to form nanostructures, determines the scallop size. and the oxidation process is performed for about 70 min to isolate each layer by completely oxidizing Appl. Sci. 2020, 10, x FOR PEER REVIEW 10 of 10 (d) (e) (f) Si SiO PR Wet Oxidation Figure 2. Fabrication process flow. (a) TEOS deposition; (b) PR patterning using UV lithography; (c) Appl. Sci. 2020, 10, 1146 5 of 10 TEOS patterning; (d) PR removal; (e) DRIE for fabricating protrusion and support structure; (f) wet oxidation for nanowire fabrication and layer-to-layer isolation. the support structure. The additional oxidation is 20–25% more than the width of the support structure Table 1. DRIE process steps for process development. because the rate of oxidation is slower than the surface. Gas Flow Table 1. DRIE process steps for process development. Coil Power Platen Power Pressure (sccm) Time (s) (W) (W) (mTorr) Gas Flow (sccm) Coil Platen Pressure C4F8 SF6 Ar Time (s) (mTorr) Power (W) Power (W) C F SF Ar 4 8 6 Polymer 825 1 22 100 0.5 30 5 Polymer deposition 825 1 22 100 0.5 30 5 deposition Polymer etch 825 13 23 0.5 50 30 3 Polymer etch 825 13 23 0.5 50 30 3 Silicon etch 825 13 23 0.5 100 30 5, 7, 10, 15, 18 5, 7, 10, 15, Silicon etch 825 13 23 0.5 100 30 After removing the TEOS and thermal oxide layers by hydrofluoric (HF)-acid dipping, the vertically-stacked silicon-nanowire arrays are formed. The number of vertical layers can be adjusted 3. Fabrication Results by the number of DRIE-process cycles without additional masking or photolithography processes. For the fabrication of vertically-stacked silicon-nanowire arrays, it is necessary to define a 3. Fabrication Results structure with protrusion and support, as shown in Figure 3. Indeed, the difference between the For the fabrication of vertically-stacked silicon-nanowire arrays, it is necessary to define a structure protrusion and support widths determines the wet-oxidation process time, which, in turn, with protrusion and support, as shown in Figure 3. Indeed, the di erence between the protrusion and determines the dimensions of the silicon nanowires fabricated in the protrusion. In addition, if the support widths determines the wet-oxidation process time, which, in turn, determines the dimensions width of the support is too narrow, or if the support does not form, then the thermal oxide layer will of the silicon nanowires fabricated in the protrusion. In addition, if the width of the support is too not grow uniformly during the wet-oxidation process. Therefore, the most critical step of the narrow, or if the support does not form, then the thermal oxide layer will not grow uniformly during proposed fabrication method is the DRIE process, especially the isotropic-silicon etching step, which the wet-oxidation process. Therefore, the most critical step of the proposed fabrication method is the determines the scallop size. DRIE process, especially the isotropic-silicon etching step, which determines the scallop size. Figure 3. Fabrication result after DRIE, showing silicon protrusions and supports. The experimental results of the DRIE process with the tuning of the isotropic-silicon etching time are shown in Figure 4 and summarized in Table 2. By adjusting the duration of the silicon etching, the size and depth of the scallop can be adjusted. A deep and wide scallop size can be obtained by a long silicon etching time. To find the optimal process conditions, the duration of the silicon-etching step is divided into five conditions: 5, 7, 10, 15, and 18 s. After the DRIE process, cross-sectional SEM imaging is performed to measure the protrusion width (W ), vertical gap between protrusions (H ) P P and the support width (W ) for the isotropic silicon etching results. As a result, the etch rates for W , H and W are measured to be 0.04, 0.12, and 0.07 m/s, respectively. Among the five process P P S conditions, a suitable condition for the di erence in width between the protrusion and the support is determined through experimentation. Indeed, a silicon-etching time of 15 s produces an adequate scallop size for the fabrication of the vertically-stacked silicon nanowires. Appl. Sci. 2020, 10, x FOR PEER REVIEW 10 of 10 Figure 3. Fabrication result after DRIE, showing silicon protrusions and supports. The experimental results of the DRIE process with the tuning of the isotropic-silicon etching time are shown in Figure 4 and summarized in Table 2. By adjusting the duration of the silicon etching, the size and depth of the scallop can be adjusted. A deep and wide scallop size can be obtained by a long silicon etching time. To find the optimal process conditions, the duration of the silicon-etching step is divided into five conditions: 5, 7, 10, 15, and 18 s. After the DRIE process, cross-sectional SEM imaging is performed to measure the protrusion width (WP), vertical gap between protrusions (HP) and the support width (WS) for the isotropic silicon etching results. As a result, the etch rates for WP, HP and WS are measured to be 0.04, 0.12, and 0.07 μm/s, respectively. Among the five process conditions, a suitable condition for the difference in width between the protrusion and the support is determined through experimentation. Indeed, a silicon-etching time of 15 s produces an adequate Appl. Sci. 2020, 10, 1146 6 of 10 scallop size for the fabrication of the vertically-stacked silicon nanowires. (a) (b) (c) (d) (e) (f) Figure 4. Figure 4. Ex Experimental perimental resu results lts of of the the DRI DRIE E process process with with v various arious iisotr sotropi opic-silicon c-silicon et etching ching tim times. es. (( aa ) ) Dimension parameters; Dimension parameters; ((b b) 5 ) 5 s s (ty (typical pical Bo Bosch sch process process ca case); se); ( (c c) 7 ) 7 s; ( s; (d d) ) 10 10 s; ( s; (e e) 15 s; ) 15 s; ( (f f) 18 ) 18 s. s. Table 2. Measurement results after various time duration during the DRIE process. Etching Time (s) 5 7 10 15 18 Protrusion width (W ) (m) 1.74 1.59 1.50 1.37 1.19 Vertical gap between 0.75 1.02 1.33 1.75 2.46 protrusions (H ) (m) Support width (W ) (m) 1.19 0.95 0.72 0.43 - In Figure 5, the fabrication results of the vertically-stacked silicon-nanowire arrays are presented. As is well known, for oxidation with lower oxide thickness, the rate of oxide growth is much faster than that predicted by the Deal–Grove model [24]. However, in the case of oxidation of a certain thickness, there is a region with almost linear characteristics. In this paper, the conditions that can Appl. Sci. 2020, 10, x FOR PEER REVIEW 10 of 10 Table 2. Measurement results after various time duration during the DRIE process. Etching Time (s) 5 7 10 15 18 Protrusion width (WP) (μm) 1.74 1.59 1.50 1.37 1.19 Vertical gap between protrusions (HP) (μm) 0.75 1.02 1.33 1.75 2.46 Support width (WS) (μm) 1.19 0.95 0.72 0.43 - In Figure 5, the fabrication results of the vertically-stacked silicon-nanowire arrays are presented. As is well known, for oxidation with lower oxide thickness, the rate of oxide growth is much faster t Appl. Sci. 2020, 10 h,an that pred 1146 icted by the Deal–Grove model [24]. However, in the case of oxidation of 7 of 10 a certain thickness, there is a region with almost linear characteristics. In this paper, the conditions that can grow 500 nm oxide for the fabrication of silicon nanowires having a width of approximately grow 500 nm oxide for the fabrication of silicon nanowires having a width of approximately 300 nm 300 nm are conducted with a process time between 60 and 90 min. Of course, when the oxidation are conducted with a process time between 60 and 90 min. Of course, when the oxidation thickness thickness becomes thick, and thus the oxidation process takes a long time, non-linear characteristics becomes thick, and thus the oxidation process takes a long time, non-linear characteristics are exhibited are exhibited as the silicon consumed decreases. Therefore, if possible, the width of the pattern should as the silicon consumed decreases. Therefore, if possible, the width of the pattern should be reduced be reduced during the initial UV lithography process, and a suitable scallop size should be produced during the initial UV lithography process, and a suitable scallop size should be produced to form silicon to form silicon nanowires of the desired thickness. In the process developed in this study, the UV nanowires of the desired thickness. In the process developed in this study, the UV lithography and the lithography and the PR films form a pattern width that is narrower than the line width of the mask. PR films form a pattern width that is narrower than the line width of the mask. In addition, with the In addition, with the repeated experiments, the process secures its reproducibility. In Figure 5ab, the repeated experiments, the process secures its reproducibility. In Figure 5a,b, the fabrication results fabrication results after the optimum wet-oxidation and excessive wet-oxidation are shown, after the optimum wet-oxidation and excessive wet-oxidation are shown, respectively. As can be seen respectively. As can be seen in Figure 5ab, an appropriate width difference between the protrusion in Figure 5a,b, an appropriate width di erence between the protrusion and the support is vital with and the support is vital with respect to forming a silicon nanowire with uniform dimensions. In respect to forming a silicon nanowire with uniform dimensions. In addition, the wet-oxidation process addition, the wet-oxidation process time is recommended to proceed for the minimum time required time is recommended to proceed for the minimum time required for layer-to-layer isolation. In case of for layer-to-layer isolation. In case of excessive wet oxidation, narrow silicon nanowires can form; excessive wet oxidation, narrow silicon nanowires can form; however, deviations in the dimensions however, deviations in the dimensions increase accordingly. Figure 6 shows the silicon-nanowire increase accordingly. Figure 6 shows the silicon-nanowire structures released after completion of the structures released after completion of the wet oxidation process. As shown in Figure 6a, after wet wet oxidation process. As shown in Figure 6a, after wet oxidation, the supporting part is completely oxidation, the supporting part is completely oxidized and removed by HF-acid dipping, indicating oxidized and removed by HF-acid dipping, indicating that each silicon nanowire is formed individually. that each silicon nanowire is formed individually. In Figure 6b, it can be seen that an array of silicon In Figure 6b, it can be seen that an array of silicon nanowires having a length of approximately 20 m nanowires having a length of approximately 20 μm is formed, and a silicon-nanowire array consisting is formed, and a silicon-nanowire array consisting of three vertically-stacked layers can be seen from of three vertically-stacked layers can be seen from the cross-sectional SEM image. However, after the the cross-sectional SEM image. However, after the release of the silicon nanowires, it is dicult to release of the silicon nanowires, it is difficult to verify the uniformity of the cross-sectional width, verify the uniformity of the cross-sectional width, and the cross-sectional width can only be confirmed and the cross-sectional width can only be confirmed by SEM imaging after wet oxidation. by SEM imaging after wet oxidation. (a) Figure 5. Cont. Appl. Sci. 2020, 10, x FOR PEER REVIEW 10 of 10 Appl. Sci. 2020, 10, 1146 8 of 10 Appl. Sci. 2020, 10, x FOR PEER REVIEW 10 of 10 (b) (b) Figure 5. Fabrication of vertically-stacked silicon-nanowire array. (a) Cross-sectional view (oxidation for exact t Figure 5. Figure 5. Fabri iFabrication me); ( cation of b) cros of s-se verti vertic ctico ally-stack ally-stacked nal view (ex ed silicon-nanowire silicon-nanowir cessive wet-oxid eation array. arraycase) . ((a a) Cross ) Cr . oss-sectional -sectional v viiew ew (ox (oxidation idation for exact t for exact time); ime); ( (b b) ) cros cross-sectional s-sectional view view (ex (excessive cessive wet- wet-oxidation oxidation case). case). (a) (b) (a) (b) Figure 6. Fabrication result after oxide-layer removal. (a) Released silicon-nanowire array; (b) top- Figure 6. Fabrication result after oxide-layer removal. (a) Released silicon-nanowire array; (b) top-view view and Figure 6. cros Fabri s-c secti ation onal v resuilt ew af (inset) ter oxide of re -layer removal leased structu . ( ra e.) Released silicon-nanowire array; (b) top- and cross-sectional view (inset) of released structure. view and cross-sectional view (inset) of released structure. 4. Discussion and Conclusions 4. Discussion and Conclusions 4. Discussion and Conclusions In this paper, a novel top-down method for fabricating vertically-stacked silicon-nanowire arrays In this paper, a novel top-down method for fabricating vertically-stacked silicon-nanowire was presented. This method enables the fabrication of lateral silicon-nanowire arrays in a vertical arrays In t wa hs p is pape resent r, ed. Th a novel is met top-down hod en met ables t hod he f for ab f ricat abric ion of ating vert lateral ical sily- licon sta-cke nanowir d silicon-n e arraays nowir in ae direction, as well as the fabrication of an increased number of silicon nanowires on a finite dimension, arrays was presented. This method enables the fabrication of lateral silicon-nanowire arrays in a vertical direction, as well as the fabrication of an increased number of silicon nanowires on a finite which, in turn, results in increased sensitivity and a dynamic range. This paper also deals with dimens verticalion, w direct h ion, ich, in as wel turn, l a resu s thlt e s in fabr incr icatease ion of d sen an incr sitivease ity and d n a d umber of ynamic r silic ange on n . Ta hnowires is paper a on lso a dea finit ls e the considerations in each process when manufacturing nanowires with di erent dimensions. The dimension, which, in turn, results in increased sensitivity and a dynamic range. This paper also deals with the considerations in each process when manufacturing nanowires with different dimensions. proposed fabrication process used single UV lithography, DRIE, and wet-oxidation processes. First, the The proposed fabr with the considerations ication process u in each process sed sing when ma le UVnufacturing nan lithography, DRIE, owires w and wet ith different d -oxidation pr imensions. ocesses. patterns of the silicon-nanowire array were defined by photolithography. However, the UV lithography The proposed fabrication process used single UV lithography, DRIE, and wet-oxidation processes. First, the patterns of the silicon-nanowire array were defined by photolithography. However, the UV has limited resolution, so the number of silicon nanowires that can be fabricated per unit area is limited. lit Fihogr rst, the pa aphy h tterns of the as limited re sil sio con- lution nanowi , so th re array we e number o re f s d ili efine con n d by anow pho ires t tolit hhograph at can be y f . How abricat ever, ed p te h r e U unit V The silicon-nanowire arrays in this paper were fabricated at the wafer-level and used as one building lithography has limited resolution, so the number of silicon nanowires that can be fabricated per unit area is limited. The silicon-nanowire arrays in this paper were fabricated at the wafer-level and used block for the purpose of integration with other electronic devices. Therefore, this paper dealt with a as one area is bu limild ited. The ing block silicon for -nanow the purpose ire arrof int ays in t egh rat is p ion aper were with other e fabricat lectronic d ed at the evices. Ther wafer-levelefor and us e, this ed process method of increasing the number of silicon nanowires per unit area by vertically stacking to as one building block for the purpose of integration with other electronic devices. Therefore, this paper dealt with a process method of increasing the number of silicon nanowires per unit area by improve the sensing characteristics. Then, the structures in which the silicon nanowires form were vert paper icadealt lly stawith a process method of increa cking to improve the sensing chsing th aracteri e number of silicon stics. Then, the struct nanow ures in which t ires per unit hearea by silicon defined by DRIE, where the number of vertically-stacked arrays can be adjusted by the number of vertically stacking to improve the sensing characteristics. Then, the structures in which the silicon nanowires form were defined by DRIE, where the number of vertically-stacked arrays can be adjusted dry-etching repetitions. Finally, the silicon nanowires were formed through a wet-oxidation process, by the numbe nanowires forr m of were d dry-etching repetition efined by DRIE, where the n s. Finally, the umber of ve silicon na rtic nowires were fo ally-stacked array rmed through s can be adjusted a wet- where the silicon-nanowire dimensions can be precisely controlled by the process time. The uniformity by the number of dry-etching repetitions. Finally, the silicon nanowires were formed through a wet- oxidation process, where the silicon-nanowire dimensions can be precisely controlled by the process oxidation process, where the silicon-nanowire dimensions can be precisely controlled by the process Appl. Sci. 2020, 10, 1146 9 of 10 of the silicon nanowires created on each layer is, in turn, most a ected by the uniformity of the scallop with the depth of the DRIE process. Through various experiments in this paper, the process conditions in which the scallop can be produced most uniformly according to depth were derived, and the size of the protrusion and support produced when it was done in accordance with this condition were measured and evaluated. Depending on the oxidation process time, the dimension of the silicon nanowires is also a ected. To this end, we measured the width of the protrusion and support and conducted the oxidation process only for the optimal time for isolating the layer. Figure 5 discusses the possible imbalance when the oxidation process is carried out for the optimum time and excessive time. Using the proposed method, the fabrication results of the vertically-stacked silicon-nanowire array consisting of three vertical layers are shown. It is expected that the amount of current output from the sensor can be increased when implementing chemical or optical sensors using it. Each layer is equipped with twenty well-aligned diamond-shaped silicon nanowires with the dimensions of a single nanowire of approximately 300 nm in width and 20 m in length. Indeed, this should lead to highly sensitive, reproducible, and low-cost silicon-nanowire sensors that can be used for a number of applications. In this paper, we created a three-layered silicon-nanowire array, but using this process, it is possible to produce more than three layers. The latest DRIE equipment is capable of deep silicon etching with a scale of up to tens of um uniform size scallops, and the depth of the silicon-nanowire array on the third floor produced in this paper is approximately 5 m. Therefore, the proposed method is expected to fabricate silicon-nanowire arrays with a more vertically-stacked structure. In addition, the proposed method can reduce the process complexity and facilitate monolithic integration when combining silicon nanowire-based sensors and CMOS circuits. Author Contributions: S.L. conceptualized and supervised the study; K.K., J.K.L. and S.J.H. designed and fabricated the device; all authors participated in the evaluations; and S.L. and K.K. wrote the paper. All authors have read and agreed to the published version of the manuscript. Funding: This research and the APC was supported by the Practical Technology Development Medical Microrobot Program (R&D Center for Practical Medical Microrobot Platform, HI19C0462) funded by the Ministry of Health and Welfare (MOHW, Korea) and Korea Health Industry Development Institute (KHIDI, Korea). Acknowledgments: The device fabrication was supported by the Inter-University Semiconductor Research Center (ISRC), Republic of Korea. Conflicts of Interest: The authors declare no conflict of interest. References 1. Zhai, T.; Li, L.; Ma, Y.; Liao, M.; Wang, X.; Fang, X.; Yao, J.; Bando, Y.; Golberg, D. One-dimensional inorganic nanostructures: Synthesis, field-emission and photodetection. Chem. Soc. Rev. 2011, 40, 2986. [CrossRef] 2. Wang, Y.; Herron, N. Nanometer-sized semiconductor clusters: Materials synthesis, quantum size e ects, and photophysical properties. J. Phys. Chem. 1991, 95, 525–532. [CrossRef] 3. Lu, W.; Lieber, C.M. Semiconductor nanowires. J. Phys. D Appl. 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Metal-Assisted Chemical Etching of Silicon: A Review. Adv. Mater. 2010, 23, 285–308. [CrossRef] 18. Miao, B.; Zhang, J.; Ding, X.; Wu, N.; Lu, W.; Li, J. Improved metal assisted chemical etching method for uniform, vertical and deep silicon structure. J. Micromech. Microeng. 2017, 27. [CrossRef] 19. In, C.; Seo, J.; Kwon, H.; Choi, J.; Sim, S.; Kim, J.; Kim, T.; Lee, T.; Choi, H. Counterbalanced E ect of Surface Trap and Auger Recombination on the Transverse Terahertz Carrier Dynamics in Silicon Nanowires. IEEE Trans. Terahertz Sci. Technol. 2015, 5, 1–8. [CrossRef] 20. Shin, J.C.; Zhang, C.; Li, X. Sub-100 nm Si nanowire and nano-sheet array formation by MacEtch using a non-lithographic InAs nanowire mask. Nanotechnology 2012, 23. [CrossRef] 21. Hashemi, P.; Canonico, M.; Yang, J.K.; Gómez, L.; Berggren, K.K.; Hoyt, J. Fabrication and Characterization of Suspended Uniaxial Tensile Strained-Si Nanowires for Gate-All-Around Nanowire n-MOSFETs. In Proceedings of the 214th ECS Meeting, Honolulu, HI, USA, 12–17 October 2008; Volume 16, pp. 57–68. 22. Lee, S. Simulation on Junctionless Silicon Nanowire Devices for Implementation of Photodetection Circuit in Retinal Prosthesis. Sens. Mater. 2019, 31, 1657–1666. [CrossRef] 23. Pogge, H.B.; Bondur, J.A.; Burkhardt, P.J. Reactive Ion Etching of Silicon With Cl2/Ar(1). J. Electrochem. Soc. 1983, 130, 1592–1597. [CrossRef] 24. Irene, E.A. Silicon oxidation studies: A revised model for thermal oxidation. J. Appl. Phys. 1983, 54. [CrossRef] © 2020 by the authors. Licensee MDPI, Basel, Switzerland. This article is an open access article distributed under the terms and conditions of the Creative Commons Attribution (CC BY) license (http://creativecommons.org/licenses/by/4.0/). http://www.deepdyve.com/assets/images/DeepDyve-Logo-lg.png Applied Sciences Multidisciplinary Digital Publishing Institute

A Novel Top-Down Fabrication Process for Vertically-Stacked Silicon-Nanowire Array

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applied sciences Article A Novel Top-Down Fabrication Process for Vertically-Stacked Silicon-Nanowire Array Kangil Kim, Jae Keun Lee, Seung Ju Han and Sangmin Lee * Department of Biomedical Engineering, Kyung Hee University, Yongin 17104, Korea; kimkangil@khu.ac.kr (K.K.); wormsvkvk@khu.ac.kr (J.K.L.); sscandidate22@khu.ac.kr (S.J.H.) * Correspondence: sangmlee@khu.ac.kr; Tel./Fax: +82-31-201-2568 Received: 19 December 2019; Accepted: 4 February 2020; Published: 8 February 2020 Abstract: Silicon nanowires are widely used for sensing applications due to their outstanding mechanical, electrical, and optical properties. However, one of the major challenges involves introducing silicon-nanowire arrays to a specific layout location with reproducible and controllable dimensions. Indeed, for integration with microscale structures and circuits, a monolithic wafer-level process based on a top-down silicon-nanowire array fabrication method is essential. For sensors in various electromechanical and photoelectric applications, the need for silicon nanowires (as a functional building block) is increasing, and thus monolithic integration is highly required. In this paper, a novel top-down method for fabricating vertically-stacked silicon-nanowire arrays is presented. This method enables the fabrication of lateral silicon-nanowire arrays in a vertical direction, as well as the fabrication of an increased number of silicon nanowires on a finite dimension. The proposed fabrication method uses a number of processes: photolithography, deep reactive-ion etching, and wet oxidation. In applying the proposed method, a vertically-aligned silicon-nanowire array, in which a single layer consists of three vertical layers with 20 silicon nanowires, is fabricated and analyzed. The diamond-shaped cross-sectional dimension of a single silicon nanowire is approximately 300 nm in width and 20 m in length. The developed method is expected to result in highly-sensitive, reproducible, and low-cost silicon-nanowire sensors for various biomedical applications. Keywords: silicon nanowire; top-down fabrication; monolithic process; vertically-stacked array 1. Introduction Silicon nanowires are widely used for sensing applications due to their outstanding mechanical, electrical, and optical properties. Accordingly, research is currently being conducted on the physical properties of silicon nanowires, as well as on their manufacturing methods and applications [1–5]. Indeed, technology is being developed to use silicon nanowires as sensing elements, with further research being conducted in terms of possible integration with complementary metal-oxide-semiconductor (CMOS) circuits [6,7]. In the case of silicon nanowires, the physical and chemical properties are largely dependent on the surface-to-volume ratio and the quantum-size e ect, which are atypical compared with conventional macroscale materials [8]. Since the surface-to-volume ratio is enormous in the nanoscale dimension, sensing apparatuses that consist of nanostructures exhibit ultrasensitive properties for surface changes. This possibility has resulted in many methods of fabricating silicon nanowire-based biosensing platforms, all of which provide label-free and highly responsive sensing in real time [9–13]. Thus, a sensor platform with highly-sensitive silicon nanowires is a viable alternative; moreover, it can facilitate the combination of multiple functions within a single sensor using the same structure of silicon-nanowire building blocks [14]. Appl. Sci. 2020, 10, 1146; doi:10.3390/app10031146 www.mdpi.com/journal/applsci Appl. Sci. 2020, 10, 1146 2 of 10 The major challenge for sensor applications of silicon nanowires is to introduce silicon-nanowire arrays to a specific layout location with reproducible and controllable dimensions. However, the bottom-up fabrication method of silicon nanowires using the metallic-catalyst growth method has diculties with respect to the exact positioning of nanowires. In addition, due to the randomly oriented growth and inconsistent distribution of the required dimensions, the control of structural parameters is also an issue that needs to be resolved [15]. In addition, many researchers have reported nanostructure fabrication using metal-assisted chemical etching processes [16–18]. This is a method to fabricate nanostructures of vertically-aligned structures by patterning metal on the substrate. This makes it possible to fabricate well-aligned vertical nanostructures according to patterned metals, but for fabrication of laterally-aligned silicon-nanowire arrays, the aligned structures can be deformed during substrate transfer [19], or the separation of nanostructures from the substrate can be dicult [20]. The Si/SiGe epitaxy method has also been reported to fabricate the nanowire [21]. The epitaxial method allows for very tight control of the film thickness; however, the stacked epitaxial layers require careful control on the film stress to obtain reproducible electrical characteristics. Among the alternative fabrication approaches, the most promising technique is based on the top-down fabrication of silicon nanowires on a silicon-on-insulator (SOI) substrate. For sensors using silicon nanowires as a sensing structure, the sensor characteristics are determined according to the dimensions of the nanowires, which must to be controllable within the tunable range of electronics. In previous studies, a method of fabricating silicon nanowires by defining a pattern width by e-beam lithography (EBL) on an SOI wafer with a thin top layer has been reported [4]. In addition, silicon nanowires can be fabricated by defining microscale patterns using conventional ultraviolet (UV) lithography and then narrowing the pattern width through wet oxidation processes [5,6,22]. As a result of our previous work, we reported on the fabrication of silicon nanowires using (100)- and (111)-single crystalline silicon, as shown in Figure 1. The authors fabricated junctionless FETs and photodetectors using silicon nanowires fabricated from top-down methods. The results of the previously reported papers confirm that the number of silicon nanowires a ects the sensor characteristics rather than the morphology of individual nanowires [22]. The fabrication method developed herein is based on a number of processes: UV lithography, silicon dry-etching, anisotropic wet-etching, and thermal oxidation. The UV lithography has an advantage in terms of cost and wafer-level process rather than E-beam lithography. In addition, this process has advantages in terms of the substrate transfer process for manufacturing flexible electronic devices, as shown in our previous papers. The width of the silicon nanowire is defined according to the precisely-controlled wet-oxidation time. Figure 1 shows the fabrication of a laterally aligned silicon-nanowire array in a single layer. However, for sensors that use silicon-nanowire structures, both sensitivity and dynamic range depend on the number and dimension of silicon nanowires. Indeed, according to the aforementioned methods, increasing the number of silicon nanowires to improve overall performance inevitably increases the size of the device in question. In this paper, a novel top-down method for fabricating vertically-stacked silicon-nanowire array is presented. Compared to previous results, this method enables the fabrication of lateral silicon-nanowire arrays in a vertical direction, thereby enabling an increased number of silicon nanowires on a finite dimension, which, in turn, results in increased sensitivity and dynamic range. The proposed fabrication process uses a single UV lithography process, multiple deep reactive-ion etching (DRIE) processes, and a wet-oxidation process. The number and dimensions of the silicon nanowires are determined according to the DRIE-process conditions and the wet-oxidation process times; moreover, it is possible to fabricate multiple silicon nanowires at a single location by UV lithography. The remainder of this paper explains the detailed monolithic-fabrication process of vertically-stacked silicon-nanowire arrays. This is followed by a dimensional and structural analysis of the fabrication results in relation to the specific process steps. The manuscript concludes with a discussion on the implications of the method as well as the applicable areas. Appl. Sci. 2020, 10, x FOR PEER REVIEW 10 of 10 The remainder of this paper explains the detailed monolithic-fabrication process of vertically- stacked silicon-nanowire arrays. This is followed by a dimensional and structural analysis of the fabrication results in relation to the specific process steps. The manuscript concludes with a Appl. Sci. 2020, 10, 1146 3 of 10 discussion on the implications of the method as well as the applicable areas. (a) (b) Figure 1. Previously reported silicon-nanowire array fabricated by top-down processes. (a) (100) Figure 1. Previously reported silicon-nanowire array fabricated by top-down processes. (a) (100) silicon-nanowire array [5] (Reproduced with permission from Lee et al., Sensors and Materials; silicon-nanowire array [5] (Reproduced with permission from Lee et al., Sensors and Materials; published by MY K.K., 2012); (b) (111) silicon-nanowire array [6] (Reproduced with permission from published by MY K.K., 2012); (b) (111) silicon-nanowire array [6] (Reproduced with permission from Lee et al., Journal of Micromechanics and Microengineering; published by IOP Publishing 2014). Lee et al., Journal of Micromechanics and Microengineering; published by IOP Publishing 2014). 2. Fabrication Process 2. Fabrication Process The major challenge during the monolithic fabrication of a vertically-stacked silicon-nanowire The major challenge during the monolithic fabrication of a vertically-stacked silicon-nanowire array is the isolation between the layers of laterally-aligned silicon nanowires. To address this challenge, array is the isolation between the layers of laterally-aligned silicon nanowires. To address this the fabrication process proposed in this paper is based on the Bosch process [23], which is used to challenge, the fabrication process proposed in this paper is based on the Bosch process [23], which is fabricate anisotropic structures with high aspect ratios. In the Bosch process, by controlling the etching used to fabricate anisotropic structures with high aspect ratios. In the Bosch process, by controlling time for the isotropic-silicon etching step, it is possible to define the fabrication region of the silicon the etching time for the isotropic-silicon etching step, it is possible to define the fabrication region of nanowire as well as the region where the isolation layer is fabricated. By using the wet-oxidation the silicon nanowire as well as the region where the isolation layer is fabricated. By using the wet- process, which consumes silicon in order to produce silicon-dioxide (SiO ) and results in the insulation oxidation process, which consumes silicon in order to produce silicon-dioxide (SiO2) and results in layer, vertical isolation between the upper and lower layers is achieved. the insulation layer, vertical isolation between the upper and lower layers is achieved. Based on this concept, the top-down fabrication proposed in this paper is depicted in Figure 2. Based on this concept, the top-down fabrication proposed in this paper is depicted in Figure 2. As previously mentioned, it uses a combination of photolithography, DRIE, and a wet-oxidation As previously mentioned, it uses a combination of photolithography, DRIE, and a wet-oxidation process. Moreover, a p-type (111)-oriented single-crystalline silicon wafer is used, which has a diameter process. Moreover, a p-type (111)-oriented single-crystalline silicon wafer is used, which has a of 100 mm, a thickness of 525 m, and a resistivity of 1–10 Wcm. The reason for using (111)-silicon diameter of 100 mm, a thickness of 525 μm, and a resistivity of 1–10 Ω∙cm. The reason for using (111)- instead of the commonly used (100)-silicon is to allow the current to flow through the silicon nanowires silicon instead of the commonly used (100)-silicon is to allow the current to flow through the silicon rather than the bulk silicon part. In fact, (100)-silicon can also be used to fabricate laterally-aligned nanowires rather than the bulk silicon part. In fact, (100)-silicon can also be used to fabricate laterally- silicon-nanowire arrays, as our group has also reported in previous publication [5]. However, in the aligned silicon-nanowire arrays, as our group has also reported in previous publication [5]. However, case of (100)-silicon, only a single layer can be manufactured due to the orientation of the {111} plane in the case of (100)-silicon, only a single layer can be manufactured due to the orientation of the {111} and the wet etching characteristics of the silicon. In this paper, we need to implement a multiple plane and the wet etching characteristics of the silicon. In this paper, we need to implement a multiple layer-stacked array of silicon nanowires and isolate them from the silicon bulk. The (111) silicon is layer-stacked array of silicon nanowires and isolate them from the silicon bulk. The (111) silicon is suitable for isolating the nanowire from the substrate because the silicon is rapidly etched sideways suitable for isolating the nanowire from the substrate because the silicon is rapidly etched sideways during wet etching [6]. This facilitates the isolation of multilayered-nanowire array structures from during wet etching [6]. This facilitates the isolation of multilayered-nanowire array structures from the silicon bulk. First, as shown in Figure 2a, an oxide-mask layer (3000 Å thick) is deposited by a the silicon bulk. First, as shown in Figure 2a, an oxide-mask layer (3000 Å thick) is deposited by a plasma-enhanced chemical vapor deposition (PECVD) process, with a radio frequency (RF) power of plasma-enhanced chemical vapor deposition (PECVD) process, with a radio frequency (RF) power of 350 W, an O flow rate of 150 sccm, and a tetraethyl-orthosilicate (TEOS) flow rate of 150 sccm. The 350 W, an O2 flow rate of 150 sccm, and a tetraethyl-orthosilicate (TEOS) flow rate of 150 sccm. The TEOS layer is used as a passivation hard mask for bulk silicon etching. A GRX-601 (AZ Electronic TEOS layer is used as a passivation hard mask for bulk silicon etching. A GRX-601 (AZ Electronic Materials, Luxembourg) photoresist (PR) film is spin-coated on the TEOS layer with a rotation speed Materials, Luxembourg) photoresist (PR) film is spin-coated on the TEOS layer with a rotation speed of 4000 rpm and exposed to a UV light source with a wavelength of 365 nm for 3.1 s. Following the of 4000 rpm and exposed to a UV light source with a wavelength of 365 nm for 3.1 s. Following the exposure, the PR is developed in an AZ 300 MIF developer for 18 s and then rinsed in deionized (DI) water, as shown in Figure 2b. The photolithography step defines the in-plane dimension of the silicon-nanowire arrays, such as the pattern width and length. Appl. Sci. 2020, 10, x FOR PEER REVIEW 10 of 10 exposure, the PR is developed in an AZ 300 MIF developer for 18 s and then rinsed in deionized (DI) water, as shown in Figure 2b. The photolithography step defines the in-plane dimension of the silicon-nanowire arrays, such as the pattern width and length. After PR patterning, the TEOS hard-mask layer is etched by an inductive-coupled plasma (ICP) etcher with a CHF3 flow rate of 25 sccm, a CF4 flow rate of 5 sccm, and a pressure of 130 mTorr with an RF power of 600 W, as depicted in Figure 2c. The target etching thickness of the TEOS layer is calculated to be approximately 110% of the deposited thickness, which guarantees the exposure of the silicon surface. As shown in Figure 2d, after the PR strip step, a piranha solution (a mixture of sulfuric acid and hydrogen peroxide) cleaning process and an O2 plasma ashing process are conducted to remove the residuals. In Figure 2e, the bulk silicon is etched using a cyclic DRIE process, which consists of a single deposition step and two etching steps. In a conventional Bosch process, polymer deposition, polymer etching, and isotropic-silicon etching are conducted for five seconds, three seconds, and five seconds, respectively, in order to configure a high aspect-ratio structure. However, the process developed in this paper controls the final silicon etching time to fabricate the protrusion structures, which are in a location where the silicon nanowires are formed. The detailed DRIE process is summarized in Table 1. Several experiments are performed to optimize the adequate scallop size by tuning the duration of the isotropic-silicon etching step. As shown in Figure 2f, a thermal wet-oxidation process is conducted to define the width and thickness of the silicon nanowire, both of which can be precisely controlled according to the wet- oxidation time. The process is performed under a temperature of 1000 °C with an H2 flow rate of 7000 sccm and an O2 flow rate of 6500 sccm. In essence, the wet-oxidation process consumes silicon to produce thermal oxide; hence, the silicon nanowires are fabricated under a protrusion structure, while the vertical layers are isolated by the insulation layers. In this paper, Bosch 5/3/15 process is used for DRIE, and the purpose is to fabricate nanowires with a width of approximately 300 nm. The wet oxidation rate of the furnace used in this process is approximately 50 Å/min to form nanostructures, and the oxidation process is performed for about 70 min to isolate each layer by completely oxidizing the support structure. The additional oxidation is 20–25% more than the width of the support structure because the rate of oxidation is slower than the surface. After removing the TEOS and thermal oxide layers by hydrofluoric (HF)-acid dipping, the vertically-stacked silicon-nanowire arrays are formed. The number of vertical layers can be adjusted by the number of DRIE-process cycles without additional masking or photolithography processes. Appl. Sci. 2020, 10, 1146 4 of 10 Appl. Sci. 2020, 10, x FOR PEER REVIEW 10 of 10 (a) (b) (c) (d) (e) (f) Si SiO PR Wet Oxidation Figure 2. Fabrication process flow. (a) TEOS deposition; (b) PR patterning using UV lithography; (c) Figure 2. Fabrication process flow. (a) TEOS deposition; (b) PR patterning using UV lithography; (c) TEOS patterning; (d) PR removal; (e) DRIE for fabricating protrusion and support structure; (f) wet TEOS patterning; (d) PR removal; (e) DRIE for fabricating protrusion and support structure; (f) wet oxidation for nanowire fabrication and layer-to-layer isolation. oxidation for nanowire fabrication and layer-to-layer isolation. After PR patterning, the TEOS hard-mask layer is etched by an inductive-coupled plasma (ICP) Table 1. DRIE process steps for process development. etcher with a CHF flow rate of 25 sccm, a CF flow rate of 5 sccm, and a pressure of 130 mTorr with an 3 4 RF power of 600 W, as depicted in Figure 2c. The target etching thickness of the TEOS layer is calculated Gas Flow Coil Power Platen Power Pressure to be approximately 110% of the deposited thickness, which guarantees the (sccm exposur ) e of the silicon Time (s) (W) (W) (mTorr) surface. As shown in Figure 2d, after the PR strip step, a piranha solution (a mixture of sulfuric acid and C4F8 SF6 Ar hydrogen peroxide) cleaning process and an O plasma ashing process are conducted to remove the residuals. In Figure 2e, the bulk silicon is etched using a cyclic DRIE process, which consists of a single Polymer 825 1 22 100 0.5 30 5 deposition deposition step and two etching steps. In a conventional Bosch process, polymer deposition, polymer etching, and isotropic-silicon etching are conducted for five seconds, three seconds, and five seconds, Polymer etch 825 13 23 0.5 50 30 3 respectively, in order to configure a high aspect-ratio structure. However, the process developed in this paper controls the final silicon etching time to fabricate the protrusion structures, which 5, 7, 10 ar , 15 e in , a Silicon etch 825 13 23 0.5 100 30 location where the silicon nanowires are formed. The detailed DRIE process is summarized in Table 1. Several experiments are performed to optimize the adequate scallop size by tuning the duration of the isotropic-silicon etching step. 3. Fabrication Results As shown in Figure 2f, a thermal wet-oxidation process is conducted to define the width and For the fabrication of vertically-stacked silicon-nanowire arrays, it is necessary to define a thickness of the silicon nanowire, both of which can be precisely controlled according to the wet- structure with protrusion and support, as shown in Figure 3. Indeed, the d  ifference between the oxidation time. The process is performed under a temperature of 1000 C with an H flow rate of protrusion and support widths determines the wet-oxidation process time, which, in turn, 7000 sccm and an O flow rate of 6500 sccm. In essence, the wet-oxidation process consumes silicon determines the dimensions of the silicon nanowires fabricated in the protrusion. In addition, if the to produce thermal oxide; hence, the silicon nanowires are fabricated under a protrusion structure, width of the support is too narrow, or if the support does not form, then the thermal oxide layer will while the vertical layers are isolated by the insulation layers. In this paper, Bosch 5/3/15 process is used not grow uniformly during the wet-oxidation process. Therefore, the most critical step of the for DRIE, and the purpose is to fabricate nanowires with a width of approximately 300 nm. The wet proposed fabrication method is the DRIE process, especially the isotropic-silicon etching step, which oxidation rate of the furnace used in this process is approximately 50 Å/min to form nanostructures, determines the scallop size. and the oxidation process is performed for about 70 min to isolate each layer by completely oxidizing Appl. Sci. 2020, 10, x FOR PEER REVIEW 10 of 10 (d) (e) (f) Si SiO PR Wet Oxidation Figure 2. Fabrication process flow. (a) TEOS deposition; (b) PR patterning using UV lithography; (c) Appl. Sci. 2020, 10, 1146 5 of 10 TEOS patterning; (d) PR removal; (e) DRIE for fabricating protrusion and support structure; (f) wet oxidation for nanowire fabrication and layer-to-layer isolation. the support structure. The additional oxidation is 20–25% more than the width of the support structure Table 1. DRIE process steps for process development. because the rate of oxidation is slower than the surface. Gas Flow Table 1. DRIE process steps for process development. Coil Power Platen Power Pressure (sccm) Time (s) (W) (W) (mTorr) Gas Flow (sccm) Coil Platen Pressure C4F8 SF6 Ar Time (s) (mTorr) Power (W) Power (W) C F SF Ar 4 8 6 Polymer 825 1 22 100 0.5 30 5 Polymer deposition 825 1 22 100 0.5 30 5 deposition Polymer etch 825 13 23 0.5 50 30 3 Polymer etch 825 13 23 0.5 50 30 3 Silicon etch 825 13 23 0.5 100 30 5, 7, 10, 15, 18 5, 7, 10, 15, Silicon etch 825 13 23 0.5 100 30 After removing the TEOS and thermal oxide layers by hydrofluoric (HF)-acid dipping, the vertically-stacked silicon-nanowire arrays are formed. The number of vertical layers can be adjusted 3. Fabrication Results by the number of DRIE-process cycles without additional masking or photolithography processes. For the fabrication of vertically-stacked silicon-nanowire arrays, it is necessary to define a 3. Fabrication Results structure with protrusion and support, as shown in Figure 3. Indeed, the difference between the For the fabrication of vertically-stacked silicon-nanowire arrays, it is necessary to define a structure protrusion and support widths determines the wet-oxidation process time, which, in turn, with protrusion and support, as shown in Figure 3. Indeed, the di erence between the protrusion and determines the dimensions of the silicon nanowires fabricated in the protrusion. In addition, if the support widths determines the wet-oxidation process time, which, in turn, determines the dimensions width of the support is too narrow, or if the support does not form, then the thermal oxide layer will of the silicon nanowires fabricated in the protrusion. In addition, if the width of the support is too not grow uniformly during the wet-oxidation process. Therefore, the most critical step of the narrow, or if the support does not form, then the thermal oxide layer will not grow uniformly during proposed fabrication method is the DRIE process, especially the isotropic-silicon etching step, which the wet-oxidation process. Therefore, the most critical step of the proposed fabrication method is the determines the scallop size. DRIE process, especially the isotropic-silicon etching step, which determines the scallop size. Figure 3. Fabrication result after DRIE, showing silicon protrusions and supports. The experimental results of the DRIE process with the tuning of the isotropic-silicon etching time are shown in Figure 4 and summarized in Table 2. By adjusting the duration of the silicon etching, the size and depth of the scallop can be adjusted. A deep and wide scallop size can be obtained by a long silicon etching time. To find the optimal process conditions, the duration of the silicon-etching step is divided into five conditions: 5, 7, 10, 15, and 18 s. After the DRIE process, cross-sectional SEM imaging is performed to measure the protrusion width (W ), vertical gap between protrusions (H ) P P and the support width (W ) for the isotropic silicon etching results. As a result, the etch rates for W , H and W are measured to be 0.04, 0.12, and 0.07 m/s, respectively. Among the five process P P S conditions, a suitable condition for the di erence in width between the protrusion and the support is determined through experimentation. Indeed, a silicon-etching time of 15 s produces an adequate scallop size for the fabrication of the vertically-stacked silicon nanowires. Appl. Sci. 2020, 10, x FOR PEER REVIEW 10 of 10 Figure 3. Fabrication result after DRIE, showing silicon protrusions and supports. The experimental results of the DRIE process with the tuning of the isotropic-silicon etching time are shown in Figure 4 and summarized in Table 2. By adjusting the duration of the silicon etching, the size and depth of the scallop can be adjusted. A deep and wide scallop size can be obtained by a long silicon etching time. To find the optimal process conditions, the duration of the silicon-etching step is divided into five conditions: 5, 7, 10, 15, and 18 s. After the DRIE process, cross-sectional SEM imaging is performed to measure the protrusion width (WP), vertical gap between protrusions (HP) and the support width (WS) for the isotropic silicon etching results. As a result, the etch rates for WP, HP and WS are measured to be 0.04, 0.12, and 0.07 μm/s, respectively. Among the five process conditions, a suitable condition for the difference in width between the protrusion and the support is determined through experimentation. Indeed, a silicon-etching time of 15 s produces an adequate Appl. Sci. 2020, 10, 1146 6 of 10 scallop size for the fabrication of the vertically-stacked silicon nanowires. (a) (b) (c) (d) (e) (f) Figure 4. Figure 4. Ex Experimental perimental resu results lts of of the the DRI DRIE E process process with with v various arious iisotr sotropi opic-silicon c-silicon et etching ching tim times. es. (( aa ) ) Dimension parameters; Dimension parameters; ((b b) 5 ) 5 s s (ty (typical pical Bo Bosch sch process process ca case); se); ( (c c) 7 ) 7 s; ( s; (d d) ) 10 10 s; ( s; (e e) 15 s; ) 15 s; ( (f f) 18 ) 18 s. s. Table 2. Measurement results after various time duration during the DRIE process. Etching Time (s) 5 7 10 15 18 Protrusion width (W ) (m) 1.74 1.59 1.50 1.37 1.19 Vertical gap between 0.75 1.02 1.33 1.75 2.46 protrusions (H ) (m) Support width (W ) (m) 1.19 0.95 0.72 0.43 - In Figure 5, the fabrication results of the vertically-stacked silicon-nanowire arrays are presented. As is well known, for oxidation with lower oxide thickness, the rate of oxide growth is much faster than that predicted by the Deal–Grove model [24]. However, in the case of oxidation of a certain thickness, there is a region with almost linear characteristics. In this paper, the conditions that can Appl. Sci. 2020, 10, x FOR PEER REVIEW 10 of 10 Table 2. Measurement results after various time duration during the DRIE process. Etching Time (s) 5 7 10 15 18 Protrusion width (WP) (μm) 1.74 1.59 1.50 1.37 1.19 Vertical gap between protrusions (HP) (μm) 0.75 1.02 1.33 1.75 2.46 Support width (WS) (μm) 1.19 0.95 0.72 0.43 - In Figure 5, the fabrication results of the vertically-stacked silicon-nanowire arrays are presented. As is well known, for oxidation with lower oxide thickness, the rate of oxide growth is much faster t Appl. Sci. 2020, 10 h,an that pred 1146 icted by the Deal–Grove model [24]. However, in the case of oxidation of 7 of 10 a certain thickness, there is a region with almost linear characteristics. In this paper, the conditions that can grow 500 nm oxide for the fabrication of silicon nanowires having a width of approximately grow 500 nm oxide for the fabrication of silicon nanowires having a width of approximately 300 nm 300 nm are conducted with a process time between 60 and 90 min. Of course, when the oxidation are conducted with a process time between 60 and 90 min. Of course, when the oxidation thickness thickness becomes thick, and thus the oxidation process takes a long time, non-linear characteristics becomes thick, and thus the oxidation process takes a long time, non-linear characteristics are exhibited are exhibited as the silicon consumed decreases. Therefore, if possible, the width of the pattern should as the silicon consumed decreases. Therefore, if possible, the width of the pattern should be reduced be reduced during the initial UV lithography process, and a suitable scallop size should be produced during the initial UV lithography process, and a suitable scallop size should be produced to form silicon to form silicon nanowires of the desired thickness. In the process developed in this study, the UV nanowires of the desired thickness. In the process developed in this study, the UV lithography and the lithography and the PR films form a pattern width that is narrower than the line width of the mask. PR films form a pattern width that is narrower than the line width of the mask. In addition, with the In addition, with the repeated experiments, the process secures its reproducibility. In Figure 5ab, the repeated experiments, the process secures its reproducibility. In Figure 5a,b, the fabrication results fabrication results after the optimum wet-oxidation and excessive wet-oxidation are shown, after the optimum wet-oxidation and excessive wet-oxidation are shown, respectively. As can be seen respectively. As can be seen in Figure 5ab, an appropriate width difference between the protrusion in Figure 5a,b, an appropriate width di erence between the protrusion and the support is vital with and the support is vital with respect to forming a silicon nanowire with uniform dimensions. In respect to forming a silicon nanowire with uniform dimensions. In addition, the wet-oxidation process addition, the wet-oxidation process time is recommended to proceed for the minimum time required time is recommended to proceed for the minimum time required for layer-to-layer isolation. In case of for layer-to-layer isolation. In case of excessive wet oxidation, narrow silicon nanowires can form; excessive wet oxidation, narrow silicon nanowires can form; however, deviations in the dimensions however, deviations in the dimensions increase accordingly. Figure 6 shows the silicon-nanowire increase accordingly. Figure 6 shows the silicon-nanowire structures released after completion of the structures released after completion of the wet oxidation process. As shown in Figure 6a, after wet wet oxidation process. As shown in Figure 6a, after wet oxidation, the supporting part is completely oxidation, the supporting part is completely oxidized and removed by HF-acid dipping, indicating oxidized and removed by HF-acid dipping, indicating that each silicon nanowire is formed individually. that each silicon nanowire is formed individually. In Figure 6b, it can be seen that an array of silicon In Figure 6b, it can be seen that an array of silicon nanowires having a length of approximately 20 m nanowires having a length of approximately 20 μm is formed, and a silicon-nanowire array consisting is formed, and a silicon-nanowire array consisting of three vertically-stacked layers can be seen from of three vertically-stacked layers can be seen from the cross-sectional SEM image. However, after the the cross-sectional SEM image. However, after the release of the silicon nanowires, it is dicult to release of the silicon nanowires, it is difficult to verify the uniformity of the cross-sectional width, verify the uniformity of the cross-sectional width, and the cross-sectional width can only be confirmed and the cross-sectional width can only be confirmed by SEM imaging after wet oxidation. by SEM imaging after wet oxidation. (a) Figure 5. Cont. Appl. Sci. 2020, 10, x FOR PEER REVIEW 10 of 10 Appl. Sci. 2020, 10, 1146 8 of 10 Appl. Sci. 2020, 10, x FOR PEER REVIEW 10 of 10 (b) (b) Figure 5. Fabrication of vertically-stacked silicon-nanowire array. (a) Cross-sectional view (oxidation for exact t Figure 5. Figure 5. Fabri iFabrication me); ( cation of b) cros of s-se verti vertic ctico ally-stack ally-stacked nal view (ex ed silicon-nanowire silicon-nanowir cessive wet-oxid eation array. arraycase) . ((a a) Cross ) Cr . oss-sectional -sectional v viiew ew (ox (oxidation idation for exact t for exact time); ime); ( (b b) ) cros cross-sectional s-sectional view view (ex (excessive cessive wet- wet-oxidation oxidation case). case). (a) (b) (a) (b) Figure 6. Fabrication result after oxide-layer removal. (a) Released silicon-nanowire array; (b) top- Figure 6. Fabrication result after oxide-layer removal. (a) Released silicon-nanowire array; (b) top-view view and Figure 6. cros Fabri s-c secti ation onal v resuilt ew af (inset) ter oxide of re -layer removal leased structu . ( ra e.) Released silicon-nanowire array; (b) top- and cross-sectional view (inset) of released structure. view and cross-sectional view (inset) of released structure. 4. Discussion and Conclusions 4. Discussion and Conclusions 4. Discussion and Conclusions In this paper, a novel top-down method for fabricating vertically-stacked silicon-nanowire arrays In this paper, a novel top-down method for fabricating vertically-stacked silicon-nanowire was presented. This method enables the fabrication of lateral silicon-nanowire arrays in a vertical arrays In t wa hs p is pape resent r, ed. Th a novel is met top-down hod en met ables t hod he f for ab f ricat abric ion of ating vert lateral ical sily- licon sta-cke nanowir d silicon-n e arraays nowir in ae direction, as well as the fabrication of an increased number of silicon nanowires on a finite dimension, arrays was presented. This method enables the fabrication of lateral silicon-nanowire arrays in a vertical direction, as well as the fabrication of an increased number of silicon nanowires on a finite which, in turn, results in increased sensitivity and a dynamic range. This paper also deals with dimens verticalion, w direct h ion, ich, in as wel turn, l a resu s thlt e s in fabr incr icatease ion of d sen an incr sitivease ity and d n a d umber of ynamic r silic ange on n . Ta hnowires is paper a on lso a dea finit ls e the considerations in each process when manufacturing nanowires with di erent dimensions. The dimension, which, in turn, results in increased sensitivity and a dynamic range. This paper also deals with the considerations in each process when manufacturing nanowires with different dimensions. proposed fabrication process used single UV lithography, DRIE, and wet-oxidation processes. First, the The proposed fabr with the considerations ication process u in each process sed sing when ma le UVnufacturing nan lithography, DRIE, owires w and wet ith different d -oxidation pr imensions. ocesses. patterns of the silicon-nanowire array were defined by photolithography. However, the UV lithography The proposed fabrication process used single UV lithography, DRIE, and wet-oxidation processes. First, the patterns of the silicon-nanowire array were defined by photolithography. However, the UV has limited resolution, so the number of silicon nanowires that can be fabricated per unit area is limited. lit Fihogr rst, the pa aphy h tterns of the as limited re sil sio con- lution nanowi , so th re array we e number o re f s d ili efine con n d by anow pho ires t tolit hhograph at can be y f . How abricat ever, ed p te h r e U unit V The silicon-nanowire arrays in this paper were fabricated at the wafer-level and used as one building lithography has limited resolution, so the number of silicon nanowires that can be fabricated per unit area is limited. The silicon-nanowire arrays in this paper were fabricated at the wafer-level and used block for the purpose of integration with other electronic devices. Therefore, this paper dealt with a as one area is bu limild ited. The ing block silicon for -nanow the purpose ire arrof int ays in t egh rat is p ion aper were with other e fabricat lectronic d ed at the evices. Ther wafer-levelefor and us e, this ed process method of increasing the number of silicon nanowires per unit area by vertically stacking to as one building block for the purpose of integration with other electronic devices. Therefore, this paper dealt with a process method of increasing the number of silicon nanowires per unit area by improve the sensing characteristics. Then, the structures in which the silicon nanowires form were vert paper icadealt lly stawith a process method of increa cking to improve the sensing chsing th aracteri e number of silicon stics. Then, the struct nanow ures in which t ires per unit hearea by silicon defined by DRIE, where the number of vertically-stacked arrays can be adjusted by the number of vertically stacking to improve the sensing characteristics. Then, the structures in which the silicon nanowires form were defined by DRIE, where the number of vertically-stacked arrays can be adjusted dry-etching repetitions. Finally, the silicon nanowires were formed through a wet-oxidation process, by the numbe nanowires forr m of were d dry-etching repetition efined by DRIE, where the n s. Finally, the umber of ve silicon na rtic nowires were fo ally-stacked array rmed through s can be adjusted a wet- where the silicon-nanowire dimensions can be precisely controlled by the process time. The uniformity by the number of dry-etching repetitions. Finally, the silicon nanowires were formed through a wet- oxidation process, where the silicon-nanowire dimensions can be precisely controlled by the process oxidation process, where the silicon-nanowire dimensions can be precisely controlled by the process Appl. Sci. 2020, 10, 1146 9 of 10 of the silicon nanowires created on each layer is, in turn, most a ected by the uniformity of the scallop with the depth of the DRIE process. Through various experiments in this paper, the process conditions in which the scallop can be produced most uniformly according to depth were derived, and the size of the protrusion and support produced when it was done in accordance with this condition were measured and evaluated. Depending on the oxidation process time, the dimension of the silicon nanowires is also a ected. To this end, we measured the width of the protrusion and support and conducted the oxidation process only for the optimal time for isolating the layer. Figure 5 discusses the possible imbalance when the oxidation process is carried out for the optimum time and excessive time. Using the proposed method, the fabrication results of the vertically-stacked silicon-nanowire array consisting of three vertical layers are shown. It is expected that the amount of current output from the sensor can be increased when implementing chemical or optical sensors using it. Each layer is equipped with twenty well-aligned diamond-shaped silicon nanowires with the dimensions of a single nanowire of approximately 300 nm in width and 20 m in length. Indeed, this should lead to highly sensitive, reproducible, and low-cost silicon-nanowire sensors that can be used for a number of applications. In this paper, we created a three-layered silicon-nanowire array, but using this process, it is possible to produce more than three layers. The latest DRIE equipment is capable of deep silicon etching with a scale of up to tens of um uniform size scallops, and the depth of the silicon-nanowire array on the third floor produced in this paper is approximately 5 m. Therefore, the proposed method is expected to fabricate silicon-nanowire arrays with a more vertically-stacked structure. In addition, the proposed method can reduce the process complexity and facilitate monolithic integration when combining silicon nanowire-based sensors and CMOS circuits. Author Contributions: S.L. conceptualized and supervised the study; K.K., J.K.L. and S.J.H. designed and fabricated the device; all authors participated in the evaluations; and S.L. and K.K. wrote the paper. All authors have read and agreed to the published version of the manuscript. Funding: This research and the APC was supported by the Practical Technology Development Medical Microrobot Program (R&D Center for Practical Medical Microrobot Platform, HI19C0462) funded by the Ministry of Health and Welfare (MOHW, Korea) and Korea Health Industry Development Institute (KHIDI, Korea). Acknowledgments: The device fabrication was supported by the Inter-University Semiconductor Research Center (ISRC), Republic of Korea. Conflicts of Interest: The authors declare no conflict of interest. References 1. Zhai, T.; Li, L.; Ma, Y.; Liao, M.; Wang, X.; Fang, X.; Yao, J.; Bando, Y.; Golberg, D. One-dimensional inorganic nanostructures: Synthesis, field-emission and photodetection. Chem. Soc. Rev. 2011, 40, 2986. [CrossRef] 2. Wang, Y.; Herron, N. Nanometer-sized semiconductor clusters: Materials synthesis, quantum size e ects, and photophysical properties. J. Phys. Chem. 1991, 95, 525–532. [CrossRef] 3. Lu, W.; Lieber, C.M. Semiconductor nanowires. J. Phys. D Appl. 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Published: Feb 8, 2020

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