Automation
, Volume 2 (4) – Oct 11, 2021

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Article A New Transformer-Less Structure for a Boost DC–DC Converter with Suitable Voltage Stress Farzad Mohammadzadeh Shahir , Meysam Gheisarnejad * and Mohammad-Hassan Khooban Department of Electrical and Computer Engineering, Aarhus University, 8200 Aarhus, Denmark; f.m.shahir@gmail.com (F.M.S.); mhkhoban@gmail.com (M.-H.K.) * Correspondence: me.gheisarnejad@gmail.com Abstract: In this paper, a new structure is proposed for a boost dc–dc converter based on the voltage- lift (VL) technique. The main advantages of the proposed converter are its lack of transformer, simple structure, free and low input current ripple, high voltage gain capability by using an input source, suitable voltage stress on semiconductors and lower output capacitance. Herein, the analysis of the proposed converter operating and its elements voltage and current relations in continuous conduction mode (CCM) and discontinuous conduction mode (DCM) are presented, and the voltage gain of each operating mode is individually calculated. Additionally, the critical inductance, current stress of switches, calculation of passive components’ values and efﬁciency are analyzed. In addition, the proposed converter is compared with other studied boost converters in terms of ideal voltage gain in the CCM and the number of active and passive components, maximum voltage stress on semiconductors, and situation of input current ripples. The correctness of the theoretical concepts is examined from the experimental results using the laboratory prototype. Keywords: DC-DC converter; boost converter; voltage-lift technique; critical inductance Citation: Mohammadzadeh Shahir, F.; Gheisarnejad, M.; Khooban, M.-H. 1. Introduction A New Transformer-Less Structure The reduction of fossil fuels, increasing energy demands and increasing air pollution for a Boost DC–DC Converter with has created demand for energy production in the ﬁeld of renewable energies such as Suitable Voltage Stress. Automation wind turbines, solar cells and fuel cells. The structure of this kind of energy produces 2021, 2, 220–237. https://doi.org/ low level dc voltage at output, therefore, dc–dc converters are used in the structure of 10.3390/automation2040014 these types of energy resources to achieve different output voltage at the output side for different duty cycle (D) [1,2]. These types of converters are classiﬁed into isolated Received: 14 August 2021 and non-isolated categories. Control of these converters can be achieved by the pulse Accepted: 2 September 2021 width modulation (PWM) and switching frequency variation techniques [3,4]. A high- Published: 11 Oktober 2021 frequency transformer is used in the structure of the isolated converters as it makes a high level of insulation. The electrical insulation is the most important factor in selecting Publisher’s Note: MDPI stays neutral dc–dc converters, and especially in some applications such as batteries in order to provide with regard to jurisdictional claims in suitable galvanic isolation; however, using high-frequency transformers causes increases in published maps and institutional afﬁl- the size and cost [3]. On the other hand, the problem of leakage inductance and its energy iations. are other important drawbacks of these types of converters. Knowing that isolated converters have a better level of insulation than non-insulated converters, the non-isolated converters such as the conventional non-isolated boost con- verter in theory have some suitable features, such as direct connection of input inductor Copyright: © 2021 by the authors. (as ﬁlter), free current ripple, less capacitance of output capacitor and ﬁlter size, less stress Licensee MDPI, Basel, Switzerland. on the elements, higher response ratio and inﬁnite output gain for duty cycle ratio near to This article is an open access article one. However, in practice, due to electromagnetic interference (EMI) of elements and the distributed under the terms and stress between them, the switch protection against overvoltage, reverse recovery problems conditions of the Creative Commons and the stability, reduction of efﬁciency and power density, the duty cycle ratio is limited Attribution (CC BY) license (https:// to approximately 0.8 [5,6]. Therefore, new structures with different techniques have been creativecommons.org/licenses/by/ introduced to achieve higher voltage gain compared to conventional boost converters. 4.0/). Automation 2021, 2, 220–237. https://doi.org/10.3390/automation2040014 https://www.mdpi.com/journal/automation Automation 2021, 2 221 The interleaving or cascade connection technique is one of the presented techniques for increasing voltage gain [7,8]. In these techniques, the higher output voltage gain can be achieved for low duty cycle ratios. However, the converters based on these techniques have less advantages compared to conventional boost converters due to the voltage across the main switches, increasing size and cost, interference problem and complex control system. The switched-capacitor (SC) technique is the other technique which has been intro- duced to increase the output voltage gain. In this technique, a number of diodes and capacitors are combined and provide the higher output voltage and lower voltage stress. However, the current stress of switching and hard switching, high input current ripple increases the losses of the switching and conductance of active switches, reduces the efﬁ- ciency and makes the control system more complex for this type converter [9,10]. On the other hand, the current ripple is signiﬁcant in this technique. The coupled inductor or high frequency transformer technique is introduced from other techniques [11,12]. In this technique, the desired output voltage can be achieved by increasing the turn ratio of the transformer. In addition, the current stress of switching and the voltage stress across main switch are solved in this technique [13,14]. However, increasing the physical dimensions of the converters is the drawback of this method. In addition, the leakage inductance and its energy are the main problems of this technique. Even though the problem of leakage inductance and increasing the efﬁciency is solved by non-dissipative snubber or active clamp circuits [15], use of the active clamp circuit in this technique makes the control process more complex. The technique to combine multiple converters together is another technique to achieve higher voltage gain and lower voltage across switches [16,17], although its application is limited due to the balance problem of the series capacitor at output side. The other technique for boosting voltage is the switched-boost network where the impedance network has been replaced to input inductor. This method provides higher voltage gain with lower duty cycles but the high input current ripple is the main drawback of it [18]. The voltage-lift (VL) technique is another method to increase the output voltage gain that is used in many studies [19–22]. This technique is discussed for converters with periodic switching. This technique provides simpler structure, less element stress, less current ripple, high efﬁciency, high power density and lower price compared with other discussed techniques. The increasing process of this technique is step to step. In addition, the voltage multiplier cells (VMCs), which include a combination of diode and capacitor can be used to achieve higher output voltage gain [23]. As the voltage stress on the main switch is low, the Schottky diode with low reverse recovery time can be used to reduce the conduction losses. This paper proposes a new high-gain transformer-less structure for a boost dc–dc converter based on the VL technique, such as in [6,19–22], with a simple structure with suitable voltage stress on semiconductors, free and low input current ripple by using one input voltage source and lower output capacitance. Although the proposed converter and [6] has the same number of passive components (inductors and capacitors) and ideal voltage gain but the proposed converter has one less active component (one diode), its non- ideal voltage gain, total losses and efﬁciency will be improved. In this paper the following procedure will be presented: ﬁrst, the relations between voltage and current of each element in CCM and DCM are calculated as well as voltage gain in each mode. Then, the critical inductances, switching current stress, passive components value and efﬁciency calculations are discussed. In the following, the proposed converter in this paper is compared with some other presented boost converters in studies in terms of different indexes. Finally, the validity of theoretical concepts is examined by the experimental results using the laboratory prototype. Automation 2021, 2, FOR PEER REVIEW 3 indexes. Finally, the validity of theoretical concepts is examined by the experimental Automation 2021, 2 222 results using the laboratory prototype. 2. The Proposed Converter Structure 2. The Proposed Converter Structure Several voltage-lift structures for dc–dc boost converter which have been presented Several voltage-lift structures for dc–dc boost converter which have been presented in lecturers are shown in Figure 1a–c [20–22]. Additionally, the structure of the proposed in lecturers are shown in Figure 1a–c [20–22]. Additionally, the structure of the proposed converter and its drive circuit are shown in Figure 1d. As shown in Figure 1, the proposed converter and its drive circuit are shown in Figure 1d. As shown in Figure 1, the proposed converter has two power electronic switches (such as in [20,22]), two inductors (such as in converter has two power electronic switches (such as in [20,22]), two inductors (such as [20–22]), three capacitors and three diodes (such as in [20,21]) and the proposed in [20–22]), three capacitors and three diodes (such as in [20,21]) and the proposed con- converter’s driving circuits consist of a microcontroller to providing PWM and a gate verter ’s driving circuits consist of a microcontroller to providing PWM and a gate driver driver such as TLP250, a logical IC to generate the opposite PWM wave because the two such as TLP250, a logical IC to generate the opposite PWM wave because the two switches switches of the proposed converter acts as mutually opposed at a period. The transformer- of the proposed converter acts as mutually opposed at a period. The transformer-less less and simple structure, direct connection of inductor to the input with lower input and simple structure, direct connection of inductor to the input with lower input current current ripple (as filter), lower output capacitance, suitable voltage stress on ripple (as ﬁlter), lower output capacitance, suitable voltage stress on semiconductors and semiconductors and increasing step-to-step voltage to output are the features of the increasing step-to-step voltage to output are the features of the proposed converter while proposed converter while its drawback is the use of two switches that are switched its drawback is the use of two switches that are switched mutually opposed at a period. mutually opposed at a period. For the convenience of analysis, it is intended that: For the convenience of analysis, it is intended that: (a) The proposed converter is in steady state, and then the output voltage is assumed (a) The proposed converter is in steady state, and then the output voltage is assumed to to be constant; be constant; (b) The capacitors are large enough and as a result the capacitors voltage can be (b) The capacitors are large enough and as a result the capacitors voltage can be assumed assumed to be constant in each switching cycle; to be constant in each switching cycle; (c) The switches and diodes are ideal. (c) The switches and diodes are ideal. + D 2 − i L 2 D 2 D S + Do L v + 2 L 2 + − 1 L1 Do D1 L − i + − i v L1 C1 C1 C R Co D1 + Co stag e (a) D 2 L2 C1 + D 2 + − L L 2 C 1 D D1 C 1 i L C I i D L1 2 o 1 D 3 i C 2 D1 + − i + L1 − v C 3 + I − + D3 C 2 + V V C C 3 (b) Figure 1. Cont. Automation 2021, 2 223 Automation 2021, 2, FOR PEER REVIEW 4 v v i v + − − v L1 + − L2 L2 D1 + − D2 i C2 L L i I i C1 L1 1 2 D2 D D1 o v V S C C R C2 C1 S V 1 2 o (c) D I 3 o D L 2 C i + C o V 1 S S − i 2 Gate Driver Microcontroller (d) Figure 1. (a) The presented converter in [20], (b) the presented converter in [21], (c) the presented Figure 1. (a) The presented converter in [20], (b) the presented converter in [21], (c) the presented converter in [22], (d) the proposed converter. converter in [22], (d) the proposed converter. 2.1. Operating Principle 2.1. Operating Principle Here, the operating principle of the proposed converter is described with details in Here, the operating principle of the proposed converter is described with details in CCM and DCM as follows: CCM and DCM as follows: 2.1.1. The Time Intervals of T in CCM and (t , t ) in DCM: on 0 1 2.1.1. The Time Intervals of T in CCM and (,tt) in DCM: on 01 In this time interval that the switch S is turned on, the switch S is turned off, 1 2 In this time interval that the switch S is turned on, the switch S is turned off, the 1 2 the diodes of D and D are reversely biased and the D diode is directly biased, the in- 1 2 3 diodes of D and D are reversely biased and the D diode is directly biased, the 1 2 3 ductor L is directly connected to the input voltage source (V ), as a result, its current is 1 i inductor L is directly connected to the input voltage source () V , as a result, its current linearly increased from its minimum value (I ) to its maximum value (I ). During 1 LV1 i LP1 this time interval, the inductor L and the capacitors C and C are connected in series and is linearly increased from its minimum value () I to its maximum value () I . During 2 1 2 LV 1 LP1 provided the load current and the capacitor C charge current. In this case, the inductor L 3 2 this time interval, the inductor L and the capacitors C and C are connected in series 2 1 2 current is gradually decreased from its maximum value (I ) to its minimum value (I ). LP2 LV2 and provided the load current and the capacitor C charge current. In this case, the Additionally, the voltage of the capacitors C and C are decreased from their maximum 1 2 inductor L current is gradually decreased from its maximum value() I to its 2 LP2 values (V ) (V ) to their minimum values (V ) (V ). During this time interval, CP1 CP2 CV1 CV2 minimum value () I . Additionally, the voltage of the capacitors C and C are the capacitor LV 2 C voltage and its stored energy are increased from it1s minimum 2 value (V ) 3 CV3 decreased to from their maximum values its maximum value (V ). In() VDCM, () Vthis time to their interval minimum v continuesaunti lues l the() V curr ent of the CP3 CP1 CP2 CV 1 inductor L goes to zero. () V . During this time interval, the capacitor C voltage and its stored energy are CV 2 3 increased from its minimum value () V to its maximum value () V . In DCM, this time CV 3 CP3 2.1.2. The Time Interval of (t , t ) in DCM: 1 2 interval continues until the current of the inductor L goes to zero. In this time interval, the switch S is still turned on, the switch S is turned off, and the diodes of D and D are reversely biased and as the current the inductor L is zero, 1 2 2 2.1.2. The Time Interval of (,tt ) in DCM: therefore, the D diode is reversely biased as well. As a result, the inductor L current is 3 1 In thisincr time interva eased to I l, the swi . In addition, tch S is st the ill voltage turned on, t of the he swit capacitors ch S iC s tu and rned C o ,fand f, and their stored LP1 1 2 1 2 energy remain unchanged. In this condition, the load current is provided by the capacitor the diodes of D and D are reversely biased and as the current the inductor L is zero, 1 2 2 C discharge current, as a result, its voltage is gradually decreased. therefore, the D diode is reversely biased as well. As a result, the inductor L current is 3 1 Automation 2021, 2 224 2.1.3. The Time Intervals of T in CCM and (t , t ) in DCM: o f f 2 3 This interval begins when the switch S is turned off and the switch S is turned on. 1 2 In this state, the diodes of D and D are directly biased while the D diode is still reversely 1 2 3 biased. Therefore, the inductor L is connected to the inductor L and the capacitors C and 1 1 C . As a result, the inductor L current is gradually decreased to I while the inductor 2 1 LV1 L current and the voltage of the capacitors C and C is increased to their maximum 2 1 2 values. As the load current is provided by the capacitor C discharge current, therefore, the capacitor C voltage is decreased to minimum value. In DCM, this time interval continues until the current of L goes to zero. 2.1.4. The Time Interval of (t , t ) in DCM: 3 4 In this time interval, the switch S is still turned off, the switch S is turned on and the 1 2 D diode is reversely biased. Due to the fact that the inductor L current is equal to zero, 3 1 the diodes of D and D are reversely biased. Therefore, the stored energy of the inductor L and the capacitors C and C remains unchanged. On the other hand, the capacitor C 2 1 2 3 stored energy is still released to load, so, the capacitor C voltage is gradually decreased. In the following sections, indices 1 and 2 represent time intervals of T and T in on o f f CCM, respectively, and indices 1, 2, and 3 indicate time intervals of (t , t ), (t , t ) and 0 1 1 2 (t , t ) in DCM, respectively. Additionally, v and i show voltage and current, respectively. 2 3 2.2. Analysis of Proposed Converter in CCM By applying kirchhoff’s voltage law (KVL) in Figure 1d, we would have: di Di L1,1 L1 v = V = L = L (1) L1,1 i 1 1 dt T on Applying KVL in Figure 1d, the following is obtained: di Di L1,2 L1 v = V v = L = L (2) L1,2 i C1,2 1 1 dt T o f f Applying the voltage-second principle for L , deﬁning duty cycle for dc–dc converter as D = T /T and assuming sufﬁciently large capacitance for C , we get: on 1 v = V = v = v (3) C1,2 i C1 C1,1 1 D By applying KVL in Figure 1d, we get the following equation: di Di L2,1 L2 v = v + v V = L = L (4) L2,1 C1,1 C2,1 o 2 2 dt T on By applying KVL in Figure 1d, the below relation is obtained: di Di L2,2 L2,2 v = v = L = L (5) 2 2 L2,2 C2,2 dt T o f f From Figure 1d and considering sufﬁciently large capacitance for C , the following relation is obtained: v = v = v = v (6) C2 C2,1 C2,2 C1 According to Figure 1d, the following equation is obtained for the average voltage of the capacitor C : v = V (7) C3 o Automation 2021, 2, FOR PEER REVIEW 6 From Figure 1d and considering sufficiently large capacitance for C , the following relation is obtained: vv==v =v (6) CC22,1 C2,2 C1 According to Figure 1d, the following equation is obtained for the average voltage of the capacitor C : vV = (7) Co 3 Applying voltage-second principle for L and substituting (4) and (5), the voltage gain of the proposed converter in CCM is extracted as follows: Automation 2021, 2 225 V 1 + D M == (8) VD(1 −D) Applying voltage-second principle for L and substituting (4) and (5), the voltage gain Other voltage and current relations in CCM are presented in Table 1. Additionally, of the proposed converter in CCM is extracted as follows: the voltage and current waveforms of inductors in CCM are shown in Figure 2a. V 1 + D M = = (8) V D(1 D) Table 1. The voltage and current equations of elements in CCM and DCM. Other voltage and current relations in CCM are presented in Table 1. Additionally, the CCM DCM Element/Time voltage and current waveforms of inductors in CCM are shown in Figure 2a. T (,tt) (,tt ) (,tt) (,tt ) Interval on off 01 12 23 34 C ii==i ii=−i −i ii==i ii=−i −i 0 0 1 CC 1,1 2,1 L2,1 CL 1,2 1,2 L2,2 C2,2 CC 1,1 2,1 L2,1 CL 1,3 1,3 C2,3 L2,3 Table 1. The voltage and current equations of elements in CCM and DCM. C ii==i ii=−i −i ii==i ii=−i −i 0 0 2 CC 1,1 2,1 L2,1 CL 2,2 1,2 L2,2 C1,2 CC 1,1 2,1 L2,1 CL 2,3 1,3 L2,3 C1,3 CCM DCM Element/Time C ii=−I iI =− ii=−I iI =− 3 CL 3,1 2,1 o Co 3,2 CL 3,1 2,1 o Co 3,4 Interval T T (t , t ) (t , t ) (t , t ) (t , t ) on of f 0 1 1 2 2 3 3 4 D vv =− ii=+i vv =− ii=−i vV=−v 1 DC 1,1 1,1 DL 1,2 2,2 C1,2 DC 1,2 1,2 DL 1,3 1,3 C2,3 Di 1,4 C1,4 C i = i = i i = i i i i = i = i 0 i = i i i 0 1 C1,1 C2,1 L2,1 C1,2 L1,2 L2,2 C2,2 C1,1 C2,1 L2,1 C1,3 L1,3 C2,3 L2,3 C i = i = i i = i i i i = i = i 0 i = i i i 0 2 C1,1 C2,1 L2,1 C2,2 L1,2 L2,2 C1,2 C1,1 C2,1 L2,1 C2,3 L1,3 L2,3 C1,3 D vv =− −v +v ii = vv =− −v −v ii=−i −i vV=−v 2 DC 2,1 1,1 C2,1 L2,1 DC 2,2 2,2 DC 2,2 1,2 C2,2 L2,2 DL 2,3 1,3 C1,3 L2,3 Di 2,4 C2,2 C i = i I i = I i = i I i = I 3 C3,1 L2,1 o C3,2 o C3,1 L2,1 o C3,4 o D v = v i = i + i v = v i = i i v = V v 1 D1,1 C1,1 D1,2 L2,2 C1,2 D1,2 C1,2 D1,3 L1,3 C2,3 D1,4 i C1,4 D ii = vv=−V ii = vv=−V 3 DL 3,1 2,1 D3,2 Co 2,3 DL 3,1 2,1 D3,4 Co 2,4 v = i = D2,1 D2,3 D i = i v = v v v v = V v 2 D2,2 D2,2 L2,2 C2,2 C1,2 C2,2 D2,4 i C2,2 v v + v i i i L2,3 S C1,1 C2,1ii =L2,1 vV=−v ii = L1,3 vV C1,3=−v vV = 1 SL11 Si11L,2 SL11 Si11L,3 Si 1 D i = i v = v V i = i v = v V 3 D3,1 L2,1 D3,2 o D3,1 L2,1 D3,4 o C2,3 C2,4 S i = i v = V v i = i v = V v v = V 1 S1 L1 S1 L1,2 S1 L1 S1 L1,3 S1 S vv=−v i ii=+i vv=−v vv = ii i=+i vv=− i v 2 SC21,1 L2,1 SL22 C2 SC21,1 L2,1 SC21,2 SL22 C2 SC21,4 L2,4 S v = v v i = i + i v = v v v = v i = i + i v = v v 2 S2 C1,1 L2,1 S2 L2 C2 S2 C1,1 L2,1 S2 C1,2 S2 L2 C2 S2 C1,4 L2,4 L1 L1 T T on off LP1 LP1 Δi Δi L1 L1 LV1 t t t t t 0 2 4 1 3 0 t L1 L1 t 0 VV − VV − iCV 1 iCV1 VV − VV − iCP1 iCP1 i L2 L2 I LP2 LP2 Δi Δi L2 L2 LV 2 0 t L2 L2 CP2 CP1 V CV2 CV1 0 t VV−+V VV+−V CP12 o CP CP12 CP o VV−+V VV+−V CV12 o CV CV12 CV o (a) (b) Figure 2. The voltage and current waveforms for inductors: (a) in CCM; (b) in DCM. 2.3. Analysis of the Proposed Converter in DCM By applying KVL in Figure 1d, we get: di Di L1,2 L1 v = V = L = L (9) L1,2 i 1 1 dt Dt Automation 2021, 2 226 By applying KVL in Figure 1d, it is resulted that: di Di L1,3 L1 v = V v = L = L (10) L1,3 i C1,3 1 1 dt Dt At (t , t ), the inductor L voltage is equal to: 4 1 v = 0 (11) L1,4 Applying the voltage-second principle for L , deﬁning different time intervals in 0 0 0 0 DCM as D = (t t )/T, D = (t t )/T, D = (t t )/T and D = (t t )/T, 1 1 0 2 2 1 3 3 2 4 4 3 0 0 0 and duty cycle in DCM as D = D + D , the following equation is obtained for the 1 2 capacitor C : 0 0 0 D + D + D 1 2 3 v = = v = v = v = v (12) C1,3 C1,1 C1,2 C1,4 C1 By applying KVL in Figure 1d, the below relation is resulted: di Di L2,1 L2 v = v + v V = L = L (13) L2,1 C1,1 C2,1 o 2 2 dt Dt The following equation is true for the inductor L voltage at (t , t ): 2 2 v = 0 (14) L2,2 By applying KVL in Figure 1d, we have: di Di L2,4 L2 v = v = L = L (15) L2,4 C1,4 2 2 dt Dt From Figure 1d and assuming large enough capacity for C , the following equation is derived: v = v (16) C1 C2 From Figure 1d, the below relation can be resulted: v = V (17) C3 Applying the voltage-second principle for L and substituting (13) to (15), the pro- posed converter voltage gain in DCM is obtained as follows: 2 3 V 1 1 + D 1 + D 4D 4 5 M = = + + (18) V 2 D D K 2L where K = . Other voltage and current relations in DCM are presented in Table 1. Mean- RT while, the voltage and current waveforms of inductors in DCM are shown in Figure 2b. 3. Critical Inductance Calculation The boundary between CCM and DCM in a dc–dc converter can be determined by the critical inductance. In the proposed converter, the performance can be identiﬁed by determining the critical inductance L (L ) and L (L ). I + I = 0 is true for the 1 C1 2 C2 LV1 LV2 proposed converter in critical mode. Applying the current-second principle for capacitor C in CCM, the following equations can be derived: V I I = T + (19) LP2 2L D 2 Automation 2021, 2 227 Substituting (19) into (5) and considering I = 0, yields the following equation LV2 for L : C2 D (1 D)R L = (20) C2 2(1 + D) f Applying the current-second principle for capacitor C in CCM, the below relation is obtained: V V I o o I = T + (21) LP1 L V D 1 i The value of L is obtained using (2) and (21) as follows: C1 D (1 D) R L = (22) C1 2(1 + D) f According to (20) and (22), it can be concluded that L and L depends on R, f C2 C1 and D. 4. Switching Stress Calculation By appropriate selection of semiconductor elements and switches the cost of a con- verter can be reduced optimal amount. One of the key devices are power electronics switches and the calculation of peak current ﬂow switch (PCFS) can play an important role in choosing the type of switches. In the following, the PCFS for S and S are discussed. 1 2 4.1. Calculation of PCFS in CCM CCM The current of switch S (i ) is increased to its peak value (i ) at t = T and is 1 S1 on SP1 calculated as follows: CCM i = I (23) LP1 SP1 CCM The maximum PCFS of the switch S in CCM (i ) is achieved by substituting SP1,max L = L as follows: 1 C1 2V V I o o CCM i = T + (24) SP1,max DV V D i i CCM The PCFS of S in CCM (i ) at t = T is as follows: 2 on SP2 CCM i = I + i (25) LP2 C2 SP2 Using (19) and considering L = L , the maximum PCFS of the switch S in CCM 2 C2 1 CCM (i ) is obtained as follows: SP2,max V I o o CCM i = T + + i (26) C2 SP2,max D D 4.2. Calculation of PCFS in DCM DCM At t = t , the peak current ﬂow of the switch S in DCM (i ) is equal to: 2 1 SP1 DCM i = I (27) LP1 SP1 DCM At t = t , the peak current ﬂow of the switch S in DCM (i ) is as follows: 2 2 SP2 DCM i = I + i (28) LP2 C2 SP2 5. Design Consideration The calculations of the ripples of inductors current and capacitors voltage have a key role in determining the values of the inductors and capacitors, and the values of the inductors and capacitors are determined from these relations. Neglecting inductors current ripple, the root-means-square (rms) of current in CCM, I and I , are calculated L1 L2 Automation 2021, 2 228 and shown in Table 2. The allowed range for inductors current ripple, %x and %x , L1 L2 are calculated from (1) to (4) and are also shown in Table 2. Considering C = C and 1 2 jDv j = jDv j, the capacitors voltage ripple in CCM are calculated from (5) and (7). C1 C2 Table 2. Ripples calculations for inductors current and capacitors voltage. Element Relation 2 2 (1+D) D (1D) R V Di i L1 I = %x = = L1 2 L1 2 2 R I L1 D (1D) L f (1+D) D(1+D) V Di D(1D) R i L2 2 I = %x = = L2 2 L2 2 R I L2 L f (1+D) D (1D) 2 Dv D(1+D) j j (1+D)V C1 D i C = C %x = %x = = 1 2 jDv j = jDv j = C1 C2 2 C1 C2 2 v C1 2RC f D (1D) 2C f 2 1 D (1D) R Dv I (1D) j j o C3 1D jDv j = %x = = C3 C3 C f C3 RC f 3 3 6. Efﬁciency Analysis Neglecting ripples of the inductors current and the capacitors voltage, the root-mean- square (RMS) current relations of inductors and their losses are given as follows: 1 + D I = I (29) L1 o D(1 D) 1 + D I = I (30) L2 o 3D(1 D) 2 a 3 P = r I + (K f B W )(10 ) (31) ac L1 L1 L1 t f e 2 a 3 P = r I + (K f B W )(10 ) (32) L2 L2 ac t f e L2 The diodes RMS current relations are calculated as follows: 1 + D 1 I = I (33) D1 D 1 D 1 + D 1 I I = (34) D2 D (1 D) 3 1 + D 1 I I = I + I = (35) D3 C3 o 1 D D 3 P = V I + r I + 0.25Q V f (36) rr D1 F1 D1,ave D1 D1 D1 P = V I + r I + 0.25Q V f (37) D2 F2 D2,ave D2 rr D2 D2 P = V I + r I + 0.25Q V f (38) D3 F D3,ave D rr D D3 The RMS values of C and C currents are obtained as follows: 1 2 1 + D 1 I = I = I D + (39) C1 C2 o 3D 1 D Considering Q = Q , the RMS current of C current is as follows: Co Co 1 1 + D I = I + 1 D (40) C3 9D 1 D Automation 2021, 2 229 The capacitors losses are calculated as follows: P = r I (41) Cn å CN CN N=1 The switches RMS current and their losses are equal to: 1 + D 1 I = I (42) S1 1 D D 1 + D 1 2I I = (43) S2 D 1 D 3 2 2 P = r I + 0.5(t + t )I V f + 0.5C V f S1 DSon r f S1,ave S1 OSS S1 S1 (44) +0.25 f Q V + r I + V I rr,BD S1 BD1, BF1 BD1,ave BD1 2 2 P = r I + 0.5(t + t )I V f + 0.5C V f S2 DSon f S2,ave S2 OSS S2 S2 (45) +0.25 f Q V + r I + V I rr,BD S2 BD2, BF2 BD2,ave BD2 Finally, the total loss and efﬁciency are calculated as follows: P = P + P + P + P + P + P + P + P (46) Loss L1 L2 S1 S2 Cn D1 D2 D3 out h% = 100 (47) P + P out Loss 7. Comparison In this section, the proposed converter is compared with other presented boost dc–dc converters in terms of number of switches, diodes, inductors and capacitors, maximum normalized voltage stresses on switches and diodes, ideal voltage gain, input current ripple and efﬁciency. The summary of this comparison is shown in Table 3. From the number of active components (switches and diodes), the proposed converter has more active components than [9,17,21,22]. On the other hand, the active components number of the proposed converter is less than [18] and is equal to [7,20]. Of course, the proposed converter has one more switch compared to [17,21]. In terms of passive components (inductors and capacitors), the proposed converter has fewer passive components compared to [9,17,18], and has more compared to [20,22], whereas, the passive components of the proposed converter are equal to [7,21]. Such as in [7,17,20,22], the proposed converter has low input current ripple, while [9,18] has a high current ripple problem. The maximum normalized voltage stresses curve of the switches and diodes are plotted in Figure 3a,b, respectively. As seen in Figure 3a, the maximum normalized voltage stresses of the switches and diodes for the proposed converter are less than [18,20,22], and are higher that [7,17]. Additionally, the maximum normalized voltage stress of the switches for the proposed converter is more than [9] while its maximum normalized voltage stress of the diodes is less than [9]. Comparison of the ideal voltage gain variations with [7,9,17,18,20–22] is shown in Figure 3c. As illustrated, the proposed converter provides more ideal voltage gain compared to other for D < 0.5 while the ideal voltage gain of [18] is higher than the proposed converter for 0.5 < D < 0.7. For D > 0.7, the proposed converter ideal voltage gain value is more than [7,20–22] and is less than [9,17]. Automation 2021, 2, FOR PEER REVIEW 11 converter has one more switch compared to [17,21].In terms of passive components (inductors and capacitors), the proposed converter has fewer passive components compared to [9,17,18], and has more compared to [20,22], whereas, the passive components of the proposed converter are equal to [7,21]. Such as in [7,17,20,22], the proposed converter has low input current ripple, while [9,18] has a high current ripple problem. The maximum normalized voltage stresses curve of the switches and diodes are plotted in Figure 3a,b, respectively. As seen in Figure 3a, the maximum normalized voltage stresses of the switches and diodes for the proposed converter are less than [18,20,22], and are higher that [7,17]. Additionally, the maximum normalized voltage stress of the switches for the proposed converter is more than [9] while its maximum normalized voltage stress of the diodes is less than [9]. Comparison of the ideal voltage gain variations with [7,9,17,18,20–22] is shown in Figure 3c. As illustrated, the proposed converter provides more ideal voltage gain compared to other for D <0.5 while the ideal Automation 2021, 2 230 voltage gain of [18] is higher than the proposed converter for 0.5<< D 0.7 . For D >0.7 , the proposed converter ideal voltage gain value is more than [7,20–22] and is less than [9,17]. Table 3. Comparison between different converters. Table 3. Comparison between different converters. Element/Ref. [7] [9] [17] [18] [20] (n = 1) [21] [22] Proposed Active switch 2 2 1 3 2 1 2 2 Element/Ref. [7] [9] [17] [18] [20] (n = 1) [21] [22] Proposed component diode 3 2 3 12 3 3 2 3 switch 2 2 1 3 2 1 2 2 Active component Passive inductor 2 3 4 6 2 2 2 2 diode 3 2 3 12 3 3 2 3 component capacitor 3 3 6 1 2 3 2 3 inductor 2 3 4 6 2 2 2 2 Input ripple current Low High Low High Low Low Low Low Passive component ca 1pacitor 3+M3 3 6 3+M 1+2M 1 2 1+M 3 2 3+2M 3 Max. voltage stress of switches 1 1 2 4M 3M 3M 2 4M Input ripple current Low High Low High Low Low Low Low 1 3+M 3+M 1+M q 1+M 3+2M Max. voltage stress of diodes 1 2 2M 3M M 2 4M 1 1 1 3 + M 3 + M 12 + M 1 + M 32 + M 4 M Max. voltage stress of switches 1 1 2 1+3D 3D 1+5D 1 1+D 1 1+D 2 4M 3M 3M 2 4M Voltage gain in CCM (M) 1D 1D 1D 1D D(1D) 1D D(1D) D(1D) Voltage gain variation 1 3 + M 3 + M 1 + M 31 1 1 + M 32 + M 2 ! 20 1 ! 37 0 ! 27 1 ! 55 ! 11 ! 19 ! 11 ! 21 Max. voltage stress of diodes +− 1 (D : 0 ! 0.9) 2 2M 3M M 2 4M 24 M 1 1 1+ D 2 13 + D 3D 15 + D 1 + D () M Voltage gain in CCM 1 − D 1 − D 1 − D 1 − D D(1− D) 1 − D D(1− D) D(1− D) The efﬁciency changes of the proposed converter for different output power are (: D 0 →0.9) Voltage gain variation 22 → 0 13 → 7 02 → 7 15 → 5 −→11 −→19 −→11 −→ 21 shown in Figure 3d. As shown, the proposed converter has a higher calculated efﬁciency than [21,22] and its value is less than [20] for lower output power. Increasing output power, the calculated efﬁciency of the proposed converter reaches to efﬁciency value in [20,21] while its value gets much better than [22]. 1.5 [7] [18] [9] [20]&[22] [17] Proposed 0.5 2 4 6 8 10 12 14 16 18 20 (a) Figure 3. Cont. Automation 2021, 2, FOR PEER REVIEW 12 Automation 2021, 2 231 [7] [18] [9] [20] 1.5 Proposed [17] [22] 0.5 2 4 6 8 10 12 14 16 18 20 (b) [7] [18] [20]&[22] Proposed [9] [17] [21] 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 (c) [20] (n =1) η% [21] [22] Proposed(calculated) Proposed(implemented) 10 20 40 60 30 50 70 80 90 Output Power() W (d) Figure 3. Compression between different converters: (a) maximum normalized voltage stress on switches, (b) maximum Figure 3. Compression between different converters: (a) maximum normalized voltage stress on normalized voltage stress on diodes, (c) ideal voltage gain variation in versus duty ratios, (d) efficiency variations. switches, (b) maximum normalized voltage stress on diodes, (c) ideal voltage gain variation in versus duty ratios, (d) efﬁciency variations. Automation 2021, 2 232 8. Experimental Results The experimental results by laboratory prototype are used to evaluate the theoretical concepts and relations. The details of experimental laboratory prototype are presented in Table 4. It should be noted that the values of C = C and C are selected from the 2 3 common values in the market, taking into account Table 2 and %x = %x = %5 and C1 C2 %x = %1. Meanwhile, the core material of the inductors is selected the same in each C3 operating mode. Except for the critical mode and regarding section III, the inductors are designed for free current ripple conditions. In Table 4, K is the eddy current loss coefﬁcient, b is the magnetic ﬂux variation, m and n are constant and depend on the core type ac and W is core weight in grams. Powder core has been selected for all of the inductors. t f e Additionally, r , t , t , t , t , C , Q and di/dt are static drain-source on resistance, DSon r rr c OSS rr rise time, fall time, reverse recovery time, cross-over time, output capacitance, reverse recovery charge and peak diode recovery current slope, respectively. Table 4. Experimental parameters. Parameters CCM DCM L L = 3 mH; r = 0.17 W L = 35 H; r = 0.002 W 1 1 L1 1 L1 (Powder core) K = 0.00551; a = 1.23; b = 2.12; W = 44.6; B = 0.0527 K = 0.00551; a = 1.23; b = 2.12; W = 44.6; B = 0.0527 ac ac t f e t f e L L = 1.5 mH; r = 0.11 W L = 250 H; r = 0.004 W 2 2 L2 2 L2 (Powder core) K = 0.00551; a = 1.23; b = 2.12; W = 39.1; B = 0.0545 K = 0.00551; a = 1.23; b = 2.12; W = 39.1; B = 0.0545 t f e ac t f e ac C = C & C 110 F; r = 0.02 W & 63 F; r = 0.015 W 1 2 3 C1 C3 Diodes Type: MUR1560; V = 0.8 V; r = 0.01 W F,D D Type: STW45NM50F; r = 0.07 W; t = 11 nS; t = 25 nS DSon r f N-channel MOSFET t = 245 nS; t = 44 nS; C = 1260 pF; Q = 1600 nC; di/dt = 100 A/S rr c rr OSS V , f ,D,D,R 12 V, 10 kHz, 50%, 50%, 100 W Output Power 51.8 W 89.3 W 8.1. Experimental Results for Critical Mode Considering (20) and (22) and Table 4, the values of L = 69.4 H and L = 416.6 H C1 C2 are obtained. Considering L = L and L = L , the proposed converter would be in 1 C1 2 C2 critical mode. Figure 4a,b show the waveforms of current though the inductors L and L 1 2 in critical mode, respectively. If L < L and L < L then the proposed converter would 1 C1 2 C2 operates in DCM and the proposed converter operates in CCM for L > L and L > L 1 C1 C2 CCM CCM values. Substituting into Table 2 yields i = 8.15 A and i = 4 A which the SP1,max SP2,max results are veriﬁed by Figure 4c,d. 8.2. Experimental Results for CCM Considering parameters in Table 4, the proposed converter operates in CCM. Some experimental results of the voltage and current of elements are presented in Figure 5. As shown in Figure 5a, the inductor L voltage equals 12 V at T (Equation (1)) and it is on equal to 14 V at T (Equation (2)). As shown, the voltage of inductor L is equal to o f f 2 24 V and 24 V at T and T , respectively, which conﬁrmed (4) and (5). Substituting the on o f f parameters of Table 4 into (3), (6) and (8), yields v = 24 V, v = 24 V and v = 72 V. C1 C2 C3 The calculated values for the capacitors voltage are conﬁrmed by experimental results. As shown in Figure 5e,f, the current variations of the switches S and S are in accordance 1 2 CCM with Table 2. As illustrated, the PCFS of the switches S and S are equal to i = 4.5 A 1 2 SP1 CCM and i = 3 A, respectively (Equations (23) and (25)). SP2 Considering the presented parameters in Table 4 into (29) and (47), and from the third term of the diodes losses relations and ﬁfth and sixth terms of switch losses relations yields P = 2.033 W, P = 0.4352 W, P = P = 0.0512 W, P = 0.0073 W, P = 0.1849 W, L1 L2 C1 C2 C3 D1 P = P = 0.0256 W, P = 0.12943 W and P = 0.7168 W. Thus, the calculated D2 D3 S1 S2 efﬁciency is 91.4%, whereas the implemented efﬁciency is 90.6%. The calculated and imple- mented efﬁciencies for different loads are shown in Figure 3d. As shown, the calculated efﬁciency of the proposed converter is increased for higher loads and its maximum value are obtained 96.1%. Automation 2021, 2 233 8.3. Experimental Results for DCM Considering presented parameters in Table 4, the proposed converter operates in DCM. Some experimental results in this operating mode are shown in Figure 6. According to Figure 6a, the voltage variations of inductor in one period of time are in accordance with (9), (10) and (11) so that v = 12 V, v = 16 V and v = 0. Additionally, L1,2 L1,3 L1,4 the relations (13) to (15) are evaluated by experimental results in Figure 6a. As it can be seen, v = 42 V, v = 0 and v = 30 V. In addition, v = 27 V, v = 27 V L2,1 L2,2 L2,4 C1 C2 and v = 94.5 V that veriﬁes (12), (16) and (18), respectively. Furthermore, it is obtained C3 DCM DCM i = 18 A and i = 7.1 A (see Figure 6e,f) which veriﬁes the accuracy of Table 2. SP1 SP2 Table 5 shows the summery of experimental results of some parameters under CCM, critical mode and DCM. Table 5. Summary of experimental results for different operating modes. Parameters CCM Critical Mode DCM i 4.5 A 8.15 A 18 A SP1,max i 3 A 4 A 7.1 A SP2,max i - 8 A - L1,max i - 3 A - L2,max v 24 - 27 C1 Automation 2021, 2, FOR PEER REVIEW 14 v 24 - 27 C2 v 72 - 94 C3 (a) (b) (c) (d) L L S S 1 2 1 2 Figure 4. The current waveforms in a critical mode for; (a) L current, (b) L current; (c) S current, (d) S current. 1 2 1 2 Figure 4. The current waveforms in a critical mode for; (a) current, (b) current; (c) current, (d) current. 8.2. Experimental Results for CCM Considering parameters in Table 4, the proposed converter operates in CCM. Some experimental results of the voltage and current of elements are presented in Figure 5. As shown in Figure 5a, the inductor L voltage equals 12V at T (Equation (1)) and it is 1 on equal to −14V at T (Equation (2)). As shown, the voltage of inductor L is equal to off 2 24V and −24V at T and T , respectively, which confirmed (4) and (5). Substituting on off the parameters of Table 4 into (3), (6) and (8), yields vV = 24 , vV =24 and vV =72 C1 C 2 C3 . The calculated values for the capacitors voltage are confirmed by experimental results. As shown in Figure 5e,f, the current variations of the switches S and S are in 1 2 accordance with Table 2. As illustrated, the PCFS of the switches S and S are equal to 1 2 CCM CCM iA = 4.5 and iA =3 , respectively (Equations (23) and (25)). SP1 SP2 (a) (b) Automation 2021, 2, FOR PEER REVIEW 14 (a) (b) (c) (d) L L S S 1 2 1 2 Figure 4. The current waveforms in a critical mode for; (a) current, (b) current; (c) current, (d) current. 8.2. Experimental Results for CCM Considering parameters in Table 4, the proposed converter operates in CCM. Some experimental results of the voltage and current of elements are presented in Figure 5. As shown in Figure 5a, the inductor L voltage equals 12V at T (Equation (1)) and it is 1 on equal to −14V at T (Equation (2)). As shown, the voltage of inductor L is equal to off 2 24V and −24V at T and T , respectively, which confirmed (4) and (5). Substituting on off the parameters of Table 4 into (3), (6) and (8), yields vV = 24 , vV =24 and vV =72 C1 C 2 C3 . The calculated values for the capacitors voltage are confirmed by experimental results. As shown in Figure 5e,f, the current variations of the switches S and S are in 1 2 accordance with Table 2. As illustrated, the PCFS of the switches S and S are equal to 1 2 Automation 2021, 2 234 CCM CCM iA = 4.5 and iA =3 , respectively (Equations (23) and (25)). SP1 SP2 Automation 2021, 2, FOR PEER REVIEW 15 (a) (b) (c) (d) (e) (f) (g) Figure 5. Experimental results in CCM: (a) L voltage; (b) L voltage; (c) C voltage; (d) C voltage; (e) S current; (f) S Figure 5. Experimental results in CCM: (a1) L voltage; (b2 ) L voltage; (1c) C voltage; 2(d) C voltage;1 (e) S current; 2 1 2 1 2 1 current; (g) C voltage. (f) S current; (g) C voltage. 2 3 Considering the presented parameters in Table 4 into (29) and (47), and from the third term of the diodes losses relations and fifth and sixth terms of switch losses relations yields PW = 2.033 , PW =0.4352 , PP==0.0512W , PW =0.0073 , L1 L2 CC12 C3 PW =0.1849 , PP==0.0256W , PW =0.1.2943 and PW =0.7168 . Thus, the D1 DD23 S1 S 2 calculated efficiency is 91.4% , whereas the implemented efficiency is 90.6% . The calculated and implemented efficiencies for different loads are shown in Figure 3d. As shown, the calculated efficiency of the proposed converter is increased for higher loads and its maximum value are obtained 96.1% . Automation 2021, 2, FOR PEER REVIEW 16 8.3. Experimental Results for DCM Considering presented parameters in Table 4, the proposed converter operates in DCM. Some experimental results in this operating mode are shown in Figure 6. According to Figure 6a, the voltage variations of inductor in one period of time are in accordance with (9), (10) and (11) so that vV =12 , vV =−16 and v = 0 . Additionally, the L1,2 L1,3 L1,4 relations (13) to (15) are evaluated by experimental results in Figure 6a. As it can be seen, vV =−42 , v = 0 and vV =30 . In addition, vV = 27 , vV =27 and L2,1 L2,2 L2,4 C1 C 2 vV =94.5 that verifies (12), (16) and (18), respectively. Furthermore, it is obtained C 3 DCM DCM iA =18 and iA = 7.1 (see Figure 6e,f) which verifies the accuracy of Table 2. Table SP1 SP2 Automation 2021, 2 235 5 shows the summery of experimental results of some parameters under CCM, critical mode and DCM. (a) (b) (c) (d) Automation 2021, 2, FOR PEER REVIEW 17 (e) (f) (g) Figure 6. Experimental results in DCM: (a) L voltage; (b) L voltage; (c) C voltage; (d) C Figure 6. Experimental results in DCM: (a) L voltage; (b) L voltage; (c1) C voltage; (d2) C voltage; (e)1 S current; 2 2 2 1 1 1 voltage; (e) S current; (f) S current; (g) C voltage. (f) S current; (g) C voltage. 2 3 1 2 3 Table 5. Summary of experimental results for different operating modes. Parameters CCM Critical Mode DCM SP1,max 4.5a 8.15A 18A 3A 4A 7.1A SP 2,max L 1,max - 8A - - 3A - L 2,max C1 24 - 27 24 - 27 C 2 C 3 72 - 94 9. Conclusions This paper proposed a new transformer-less structure for a boost dc–dc converter with free and low input current ripple, high voltage gain capability by using an input source, lower output capacitance and suitable voltage stress on semiconductors. This new structure was proposed using the VL technique. For the proposed converter, the voltage and current relations of components were extracted in CCM and DCM in order to design purpose and the output voltage gain was calculated in each operating mode. Additionally, the critical inductance calculations of the proposed converter were presented to operate in critical mode. Moreover, current stress of switches, calculation of passive components values and efficiency are analyzed. Additionally, the proposed converter performance was compared with some other presented converters in terms of the ideal voltage gain in CCM, the number passive and active components, voltage stress on semiconductors, input current conditions and efficiency. As shown, the proposed converter has lower and suitable voltage stress on its semiconductors compared with some presented structures. Additionally, the ideal voltage gain of the proposed converter in CCM was higher than some others in more duty cycles. On the other hand, the proposed converter calculated and implemented maximum efficiencies were increased for higher loads to 96.1% and 94.8% , respectively. Of course, a drawback of the proposed converter is the use of two power electronics switches. However, the output voltage gain increased very well. The output voltage for DD== ′ 50% , VV =12 and f =10kHz in CCM and DCM are 72V CCM CCM and 94.5V , respectively. The current of switches are obtained as iA = 4.5 , iA =3 SP1 SP2 CCM CCM DCM DCM , iA =8.15 , iA =4 , iA =18 and iA = 7.1 . Finally, the performance of SP1,max SP2,max SP1 SP2 the proposed converter has been reaffirmed with mathematical and experimental results. Automation 2021, 2 236 9. Conclusions This paper proposed a new transformer-less structure for a boost dc–dc converter with free and low input current ripple, high voltage gain capability by using an input source, lower output capacitance and suitable voltage stress on semiconductors. This new structure was proposed using the VL technique. For the proposed converter, the voltage and current relations of components were extracted in CCM and DCM in order to design purpose and the output voltage gain was calculated in each operating mode. Additionally, the critical inductance calculations of the proposed converter were presented to operate in critical mode. Moreover, current stress of switches, calculation of passive components values and efﬁciency are analyzed. Additionally, the proposed converter performance was compared with some other presented converters in terms of the ideal voltage gain in CCM, the number passive and active components, voltage stress on semiconductors, input current conditions and efﬁciency. As shown, the proposed converter has lower and suitable voltage stress on its semiconductors compared with some presented structures. Additionally, the ideal voltage gain of the proposed converter in CCM was higher than some others in more duty cycles. On the other hand, the proposed converter calculated and implemented maximum efﬁciencies were increased for higher loads to 96.1% and 94.8%, respectively. Of course, a drawback of the proposed converter is the use of two power electronics switches. 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Automation – Multidisciplinary Digital Publishing Institute

**Published: ** Oct 11, 2021

**Keywords: **DC-DC converter; boost converter; voltage-lift technique; critical inductance

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