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Simulation of Multisensor Energy Data Fusion Transformer Acquisition System Based on FPGA

Simulation of Multisensor Energy Data Fusion Transformer Acquisition System Based on FPGA Hindawi International Transactions on Electrical Energy Systems Volume 2022, Article ID 7612674, 7 pages https://doi.org/10.1155/2022/7612674 Research Article Simulation of Multisensor Energy Data Fusion Transformer Acquisition System Based on FPGA 1 2 Lan Luan and Dan Hu College of Computer Science and Information, Guizhou University of Commerce, Guiyang 550025, China School of Big Data and Information Engineering, Guizhou University, Guiyang 550025, China Correspondence should be addressed to Lan Luan; 201903528@stu.ncwu.edu.cn Received 10 July 2022; Revised 30 July 2022; Accepted 4 August 2022; Published 23 August 2022 Academic Editor: Nagamalai Vasimalai Copyright © 2022 Lan Luan and Dan Hu. ,is is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited. In order to solve the problems of small signal acquisition range and poor acquisition accuracy of the existing multichannel acquisition system, a multisensor energy data fusion transformer acquisition system simulation method based on FPGA is proposed, and key hardware functions are designed and implemented. ,e system uses FPGA to control the core logic, syn- chronously collects and controls the energy data of the CCD camera and the laser rangefinder, organizes and uses an external large-capacity SDRAM group for buffering, and uses a dedicated PCI interface chip PLX9656 to achieve high-speed data transmission. Two pieces of sensor energy data and PCI bus energy data are stored in real time using a large-capacity disk array composed of multiple SATA hard disks. ,e function and performance of the energy data acquisition and storage system were tested. After the actual system test, the experimental results show that the transmission speed of the system through the PCI bus exceeds 200 MB/s, the writing speed of the continuous disk array is 240 MB/s, and the real-time acquisition and recording speed is 100 MB/ss. Conclusion. ,e system effectively solves the problems of high-speed data acquisition and storage and large capacity data transmission of key sensor nodes. energy data. With the increase of the amount of energy data 1. Introduction to be tested and the types of test energy data, it is necessary to In the research of aerospace, geological exploration, satellite collect and store multiple energy data signals at the same navigation, and other fields, it is necessary to collect and time, which puts forward higher requirements for the record some important energy data parameters for energy performance of the energy data acquisition and storage data analysis and research, which has important reference system. Because FPGA can process a large amount of parallel value for the next experiment improvement and result data at the same time, the current mainstream data acqui- analysis and is also more important for the result analysis of sition memory design schemes use FPGA as the control scientific research energy data. ,erefore, the research and module, write logic circuit programs in FPGA to control, design of energy data acquisition memory is of great sig- receive the data signals sent from the outside, and save them nificance for these fields [1]. ,e main application of data in the memory. In recent years, with the rapid development acquisition memory in these fields is to collect and record of semiconductor technology and the maturity of produc- the data collected by various sensors during the working tion technology, energy data acquisition memory has ush- process of aircraft, such as vibration signal, noise signal, ered in new development. As the main control module of image signal, and other key data. ,ese energy data play a energy data acquisition memory, large-scale integrated key role in the monitoring of aircraft operation status, fault circuits such as PGA and single chip microcomputer make analysis, environmental energy data acquisition, and so energy data acquisition and storage more complex and forth; it is very important to accurately collect and record functional by software programming. ,e products 2 International Transactions on Electrical Energy Systems developed in recent years have made great progress in 3. Research Methods multichannel energy data acquisition, large-capacity storage, 3.1. Main Functions and Technical Indicators. In the mea- high-speed storage, and so forth [2]. surement system, in order to accurately measure the jitter of ,erefore, it is of great significance to improve the the flexible baseline and the change of the relative attitude of collection and storage of real-time energy data by using the two antennas in real time, it is necessary to select a CCD emerging technologies. camera with high frame rate and large array and a high- precision laser rangefinder for combined measurement, 2. Literature Review which will produce a large amount of high-speed image energy data and distance energy data output by the laser For real-time energy data collection and storage, Miao rangefinder [8]. ,erefore, the main function of the high- et al. proposed realizing feeder automation FA by building speed acquisition and storage system designed in this paper distribution automation system (DAS) [3]. ,e meaning is to control the time synchronization between the mea- of feeder automation is to monitor the status of current, surement sensors, complete the real-time energy data ac- voltage, interconnection switch, and section switch on the quisition of each sensor, and shunt the collected energy data. feeder remotely. Yarlagadda et al. proposed updating the One channel of energy data is stored at high speed; another solid-state storage technology in the aerospace energy channel of energy data is output to another real-time pro- data storage system, changed the previous method of cessing system. According to the requirements of flexible using tape storage, and improved the stability and reli- baseline measurement system, the system in this paper ability of the energy data storage technology [4]. Kumar should be able to collect and store the measurement energy et al. proposed the integration of FPGA technology and data of two sensors in real time. ,e technical indicators to ASIC technology, so as to reduce its disadvantages of large be achieved mainly include continuous acquisition speed, volume, insufficient capacity, and larger power con- continuous storage speed, and minimum storage capacity. sumption than ASIC and then optimize energy data ,e CCD camera in the system adopts a high-resolution, transmission [5]. He et al. proposed that FPGA chip is the high frame rate area array digital camera, the image reso- core device, and online driving fatigue detection can be lution is 1608 columns ×1208 rows, and the maximum frame realized only by matching with appropriate digital image rate of the camera is 30 Hz. ,e AD sampling of the camera algorithm. ,e design omits the DSP control chip and energy data is 10 bits, and the energy data acquisition is only expands the memory to form a simplified minimum 8 bits high, so the energy data volume generated by the CCD system. Reprogrammable features and highly integrated camera per second is about 55.57 MB [9]. LRFS-0040-2 laser features can greatly reduce the design cycle and design rangefinder is used as the laser rangefinder. ,e measure- cost [6]. Tappari proposed designing the internal logic ment rate can reach 50 Hz at most. RS422 interface is used as circuit of FPGA and creating the firmware program of the energy data interface, and the amount of energy data FX3. It realizes the receiving and storage of LVDS energy generated is 9.6 kB/s. ,e energy data volume of the two data and the reading of energy data in memory by sensors per second is about 56 MB/s, so the continuous computer [7]. Kowalczyk et al. proposed using multiple acquisition speed of the acquisition system must be greater hard disks to form a RAID array (cheap redundant disk than 56 MB/s before real-time energy data acquisition of the array). High-end storage functions and redundant energy two sensors can be carried out. Only when the continuous data security were provided for large servers. Raid storage rate is greater than the acquisition speed can the combines multiple independent hard disks (physical hard energy data be stored in real time and accurately. ,erefore, disks) in different ways to form a hard disk group (logical the continuous storage speed should be greater than 56 MB/ hard disk), thus providing higher storage performance s, and the maximum theoretical read-write speed of SATA than a single hard disk and providing energy data re- hard disk can reach 150 MB/s. Using multiple SATA hard dundancy technology. disks to form a RAID array can provide higher storage According to the requirement of real-time energy data performance than a single hard disk. According to the re- acquisition and storage of key sensor nodes, this paper quirements of the flexible baseline measurement system, the proposes a solution of real-time energy data acquisition and longest continuous working time of the acquisition storage high-speed storage based on FPGA and designs and im- system is about 2 h, and the minimum storage capacity plements the key hardware functions. ,e system uses FPGA required is about 390.76 GB [10]. According to the demand for core logic control, synchronously collects and controls analysis of the above energy data acquisition system and the energy data of CCD camera and laser rangefinder, sorts considering the scalability of the system and the needs of out and uses external large capacity SDRAM group for actual energy data transmission and terminal processing, it is cache, uses a special PCI interface chip PLX9656, realizes the required that the energy data acquisition and recording high-speed transmission of two pieces of sensor energy data speed should reach 70 MB/s, the continuous disk array and PCI bus energy data, and uses a large capacity disk array writing speed should reach 120 MB/s, and the storage ca- composed of multiple SATA hard disks for real-time storage. pacity should reach 2 TB. For the 32-bit/33 MHz PCI bus, it ,e function and performance of the energy data acquisition can generally reach 80 MB/s in actual use. ,e energy data in and storage system are tested to prove the real time, stability, and out of the system memory must pass through the PCI and efficiency of the real-time energy data acquisition and bus, which will reduce the efficiency of the bus by half. ,e storage of key nodes. International Transactions on Electrical Energy Systems 3 communication interface between PCI bus and external bus acquisition speed of the system must be greater than 56 MB/ s, so the 64-bit/66 MHz PCI bus is selected, and the peak to realize the communication between them. In this system, PLX9656 is used to design high-speed PCI card to realize the speed of energy data transmission can reach 528 MB/s. ,e existing system shows that the actual transmission speed of functions of setting camera parameters, setting laser ranging the 64-bit/66 MHz PCI bus can reach more than 200 MB/s, parameters, setting sampling parameters, reading image so the transmission speed of the PCI bus fully meets the energy data, and so on. PLX9656 is the PCI interface system requirements [11]. controller with the highest performance at present. It has the ,e whole system is mainly composed of CCD camera, performance of 66 MHz and 64 bits at PCI end and 66 MHz laser rangefinder, PCI energy data acquisition card, SATA and 32 bits at local end and conforms to PCIV2.2 specifi- cation. ,e key point of PCI interface design in this system is disk array, and computer. ,e PCI image acquisition card is mainly composed of sensor energy data interface, FPGA the setting and implementation of PLX9656 local bus working mode and energy data transmission mode. ,e local logic control chip, cache, and PCI interface chip. ,e principle of the scheme is as follows: Firstly, the host sends bus of PLX9656 can be set to three modes: M mode, C mode, and J mode. According to the characteristics of the system, C commands to configure the CCD camera and laser range- finder. After the configuration is completed, the acquisition mode can be selected, and the working mode of C mode can is started. ,e high-speed image energy data output by the be realized by pulling down the pins of mode1 and mode0. In CCD camera and the synchronous control signal are sent to C mode, the energy data transmission mode is divided into the FPGA and cached in the FPGA. ,e energy data of the master mode operation, slave mode operation, and DMA laser rangefinder is also sent to the dual-port RAM of the operation. ,e DMA working mode can realize the fast FPGA through the serial port for caching. After the FIFO is transmission between high-level peripherals and memory without CPU intervention, so it is more suitable for the half full, the energy data of the CCD camera and the laser rangefinder are shunted under the control of the FPGA, one transmission of CCD camera energy data and laser range- finder energy data. ,e DMA transmission mode can be of which is sent to the external SDRAM group for caching. After the SDRAM is stored in the set image frame number, it realized by setting dmamode0/1 and PCICR of the internal registers of PLX9656 [13]. is sent to the PCI for interruption. ,e host responds to the interruption, reads the data from the SDRAM to the memory for processing, and writes the data to the hard disk 3.3. FPGA Core Logic Control to complete real-time storage. ,e other way is sent to the relevant real-time processing system for processing. ,e 3.3.1. Sensor Trigger Setting. In this design, the working block diagram of the whole design scheme is shown in modes of the two sensors are set through the host terminal, Figure 1. the mode setting string is transmitted to the FPGA through ,e design of data real-time acquisition and storage the PCI bus, and the communication with the camera and system applied to flexible baseline measurement system the laser rangefinder is realized through the serial port includes the following key technologies: CameraLink in- controller, so as to complete the configuration of the camera terface technology, multisensor synchronization technology, and the laser rangefinder. After the camera and the laser real-time acquisition and cache of multisensor data, and rangefinder receive the configuration command, the re- real-time storage of multisensor data. sponse information is also transmitted to the FPGA through the serial port controller and then transmitted to the host through the PCI bus. In order to realize the synchronous 3.2. Key Design and Implementation of Real-Time Energy Data control with the laser rangefinder, the camera selects the Acquisition and Storage System. ,e experimental camera software external trigger mode. In this mode, an EXSYNC adopts CameraLink standard interface, and the basic con- trigger signal with a frequency of 20 Hz needs to be gen- figuration adopts standard MDR26 connector output. ,e erated in the FPGA and sent to the CCD camera for ex- system uses FPGA as the main control chip of the acquisition posure reading energy data. ,e low-level width of EXSYNC card, and the i/o standard supported by FPGA is LVCMOS/ is 10 us, and the exposure time of the camera is set by the LVTTL signal [12]. ,e main function of DS90CR288A is to host terminal. complete the conversion from LVDS to TTL level signals and the conversion of serial signals into parallel signals. In order to set parameters and trigger control of the camera, it 3.3.2. Energy Data Synchronization Control. ,e EXSYNC is necessary to convert the camera control signals trigger signal is sent to the laser rangefinder and camera at (CC1–CC4) and signal SerTC (serial to camera) output from the same time to realize the output synchronization of the FPGA into LVDS signals through level conversion chip two sensors. Because the measurement speeds of the two ds90lv047 and send them to the receiver. In order to receive sensors are different, the output frame rate of the camera is the response signal (SerTFGserial-to-frame-grabber) sent by 20 frames/s, and the output frequency of the laser range- the camera to the acquisition card, ds90lv048 is used to finder is 50 Hz, so the key to the design of data synchro- convert the LVDS signal into TTL signal, which is sent to nization is how to record the single frame image data and the FPGA and sent to the host for display. laser rangefinder data at the same time. ,e timing diagram ,e system adopts 64-bit/66 MHz PCI bus to realize of the synchronous acquisition of the two sensors is shown high-speed energy data transmission. PCI interface is the in Figure 2(a). Clk100 Hz is the least common multiple of 4 International Transactions on Electrical Energy Systems SDRAM SDRAM 32M*32bit 32M*32bit SDRAM control interface PCI-X bus Write to Read FIFO FIFO PCI Cable RS422 signal Host UART Laser DB9 Interface receive/transmit DPRAM PCI Ranging interface chip interface interface RAID card controller Camera Interface DPRAM Latch FIFO link chip 1/2 SATA disk array FPGA Figure 1: Design scheme block diagram of real-time energy data acquisition and storage system. 0 0 02468 10 02468 10 Time us Time us Sensor 2 collects the timing data Sensor 1 Simulation data Sensor 1 collects the timing data Sensor 2 Simulation data (a) (b) Figure 2: Synchronous acquisition design and simulation sequence diagram of CCD camera and laser rangefinder. (a) Collect energy data. (b) Simulation energy data. simulation sequence diagram is shown in Figure 2(b) [15]. two frequencies, which can be set according to the internal resource usage of FPGA. energy data_lrf_sel is the selected According to the simulation results in Figure 2, the syn- laser energy data, where I indicates that the energy data at chronization design scheme in this paper can effectively this time is invalid, and V indicates that the energy data at reduce the delay between the two sensors and collect the this time is valid [14]. ,e energy data synchronization relative synchronization energy data of the two sensors. scheme is that after the camera energy data enters the FPGA, Although it is not strictly synchronous, it can meet the it is sorted and cached in two dual-port RAM, and the laser requirements of the flexible baseline measurement system. rangefinder sends the energy data into the FPGA through the serial port receiver. ,e serial port receiver of this design 3.3.3. Energy Data Caching and Collation. ,e caching scheme adopted in this system is to firstly latch the image has FIFO cache, and the energy data is sent to the dual-port RAM for further cache after caching. ,e write enable Wen energy data and control signal at three levels, because the image energy data output by the experimental camera is the signal of the dual-port RAM is generated according to the timing diagram shown in Figure 2(a), and the laser energy energy data of two taps, and the energy data of the two taps data is written at this time into the dual-port RAM when the are, respectively, sent to the two dual-port RAM inside the Wen signal is valid. When the read enable signal is valid, first FPGA for caching. ,e energy data of the left tap is stored the laser rangefinder energy data in the dual-port RAM is according to the sequential address, and the energy data of read into FIFO, and then the image energy data of the the right tap is stored according to the reverse address, so as corresponding frame is read into FIFO. After the FIFO is half to splice the energy data of the two taps into a complete full, the laser rangefinder energy data and camera energy image. When the enable signal is valid, the data of the two data are sent to the external SDRAM for further caching. ,e dual-port RAM is sent to FIFO for further caching. When Time sequence data Time sequence simulation data International Transactions on Electrical Energy Systems 5 disks with a capacity of 1 TB, which are configured into raid0 the FIFO data is half full, the FIFO data is sent to the external SDRAM memory through the SDRAM interface controller. mode through raid card to maximize disk access rate and form a high-speed and large capacity storage device. ,e design block diagram of the entire digital camera energy data 3.3.4. PCI Logical Interface. ,e system completes the acquisition and storage device is shown in Figure 4. ,e communication between FPGA and PLX9656 through PCI system uses the interface chip PLX9656 to send the energy local logic interface. After the system is powered on, the data output from the real-time acquisition module to the internal register of PLX9656 is reset by the RST\\\. At the system memory through the PCI bus and then writes the same time, PLX9656 outputs local reset signal LRESET and energy data in the memory into the SATA hard disk array checks whether EEPROM exists [16]. If the local DMA mode through the PCI bus under the control of the raid card. ,e is used for control, the whole handshake process is as fol- theoretical continuous disk writing speed can reach more lows: First, when the energy data in the SDRAM cache than 400 MB/s [22]. reaches the set value, the signal is valid, and the PLX9656 sends an interrupt request signal to the host. If the CPU 4. Result Analysis responds to the interrupt, it will issue the DMA read command, the number of bytes to be read, and the address In the experiment, the function and performance of the information in the corresponding program of the interrupt. system are tested, respectively. Performance test mainly PLX9656 applies for the local bus to make the LHOLD signal includes real-time acquisition and recording speed test, valid. Once again, the FPGA effective ready\\r\m signal is continuous disk array writing speed test, and stability test. enabled, and the SDRAM control interface read enable ef- For the function test of the system, the simulation image and fective signal is enabled, and the energy data begins to appear the actual image energy data acquisition test are carried out, on the LD energy data bus. When the last byte of energy data respectively. ,e analog image is the energy data with starts to be transmitted, the PLX9656 drives the blast\\ signal regular circulation generated in FPGA, and the corre- to be valid, and the FPGA has no ready\ signal [17]. Finally, sponding image is the stripe image. ,e function of the the SDRAM read enable signal is made invalid, PLX9656 acquisition system is verified according to whether the drives LHOLD to be invalid, the local bus is released, and collected energy data is correct. ,en switch to the actual then FPGA also drives LHOLDA to be invalid, ending the energy data source and collect the moving image of the primary energy data transmission. ,e design of DMA cooperative target. ,e test results of simulated and mea- transmission is shown in Figure 3. sured image energy data show that the system can collect and store energy data correctly without image dislocation, which 3.4. Cache Design and Real-Time Cache Design. Because the verifies the correctness of the system function. internal cache capacity of PCI interface chip is too small, the ,e test method for the real-time acquisition and re- cache must be used to cache the energy data in the process of cording speed of the system is as follows: because the output real-time collection and then sent to the host through PCI frequency of the sensor in the system is limited, it cannot bus to improve the transmission speed and performance of reflect the maximum acquisition and recording speed of the the system [18]. Large-capacity and high-speed SDRAM is system. Analog images of different frequencies are generated easy to buy and the price is moderate. ,e system uses in FPGA, real-time acquisition and disk writing are carried SDRAM for caching. Windows is a multithreaded and out through the system, and the image is played back by the preemptive operating system. In order to reduce the in- upper computer software to check whether there is frame terruption of threads due to the end of CPU occupation loss and dislocation. ,e measured results show that when time, the interruption interval should be greater than the the output frequency exceeds 50 Hz, if only the image is maximum thread execution time of 20 ms, so the cache collected and not saved, the image acquisition is correct, but capacity should be at least 20 ms × 70 MB/s × 2 � 2.8 MB. ,e when the disk is saved at the same time, the image dislo- caching scheme adopted by the system is to connect 2 groups cation and frame loss begin to occur. ,ere are two main of 32 m∗ 32-bit SDRAM to FPGA, which is configured by 4 reasons: One is that when the frequency is greater than 50 Hz pieces of SDRAM, and is used for energy data buffering from and the amount of energy data is greater than 100 MB/s, the camera to PCI. ,e SDRAM is encapsulated into the FIFO theoretical reading and writing speed of the external cache of interface through the controller, the camera energy data is the system is 133 MHz. Because the FIFO interface is made written into the FIFO, the interrupt is sent to PCI according to read while writing, the transmission speed is halved, to the set number of images, and then the camera energy which may lead to the cache energy data not being read in data is read by PCI, thus overcoming the shortcomings of time, resulting in image dislocation and loss. ,e other is complex SDRAM structure and difficult switching control that the read and write of the system in the host memory is a circuit [19, 20]. thread, which reads and writes energy data at the same time, Real-time streaming disk has always been the biggest resulting in the rate falling behind. To sum up, the acqui- bottleneck of high-speed energy data acquisition technology, sition and recording speed of the system can reach 100 MB/s, which directly restricts the real-time storage capacity of meeting the index requirements of 70 MB/s. acquisition and storage devices [21]. ,e system adopts PCI- ,e speed test method of continuous writing disk array is X bus motherboard supporting 66 MHz, 100 MHz, and to use a special hard disk read-write speed test software to 133 MHz/64 bits. It consists of 8 high-speed SATA hard write energy data of different capacities from the host 6 International Transactions on Electrical Energy Systems Send the Up FIFO engine PCI The DMA controls Interrupt Express the status register control Core Receive the Down FIFO engine Figure 3: DMA transmission design. Real-time storage module Data storage interface SATA disk Array PC storage PCI - X bus The data source The CCD camera Laser rangefinder Real-time acquisition module Data acquisition and cache module Camera and laser rangefinder control module Figure 4: Design of real-time high-speed storage scheme. Table 1: System stability test results. Working hours (h) 2 2 4 4 6 6 Software external Operating mode Free running Software external trigger Free running Software external trigger Free running trigger Frame loss rate (%) 0 0 0 0 0.03 0.01 memory to the disk array and average the speed of software frame loss rate of the system. ,e actual test results are statistics. ,e measured results show that the real-time shown in Table 1. It can be seen from Table 1 that, within the storage speed of the system can reach more than 240 MB/s in required working time of the system, the system has no different acquisition times, meeting the requirements of the frame loss under different modes, and the performance is very stable. Even if the working time is 3 times the required system index of 120 MB/s. In addition, the system uses 8 1 TB SATA hard disks, with a total recording capacity of time, the maximum frame loss rate of the system is only 8 TB, which meets the index requirement of 2 TB minimum 0.03%, which can meet the requirements of the measure- recording capacity of the system. ment system. ,e stability test method of the system is as follows: under different working modes, collect the energy data of 5. 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Simulation of Multisensor Energy Data Fusion Transformer Acquisition System Based on FPGA

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Copyright © 2022 Lan Luan and Dan Hu. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.
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10.1155/2022/7612674
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Hindawi International Transactions on Electrical Energy Systems Volume 2022, Article ID 7612674, 7 pages https://doi.org/10.1155/2022/7612674 Research Article Simulation of Multisensor Energy Data Fusion Transformer Acquisition System Based on FPGA 1 2 Lan Luan and Dan Hu College of Computer Science and Information, Guizhou University of Commerce, Guiyang 550025, China School of Big Data and Information Engineering, Guizhou University, Guiyang 550025, China Correspondence should be addressed to Lan Luan; 201903528@stu.ncwu.edu.cn Received 10 July 2022; Revised 30 July 2022; Accepted 4 August 2022; Published 23 August 2022 Academic Editor: Nagamalai Vasimalai Copyright © 2022 Lan Luan and Dan Hu. ,is is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited. In order to solve the problems of small signal acquisition range and poor acquisition accuracy of the existing multichannel acquisition system, a multisensor energy data fusion transformer acquisition system simulation method based on FPGA is proposed, and key hardware functions are designed and implemented. ,e system uses FPGA to control the core logic, syn- chronously collects and controls the energy data of the CCD camera and the laser rangefinder, organizes and uses an external large-capacity SDRAM group for buffering, and uses a dedicated PCI interface chip PLX9656 to achieve high-speed data transmission. Two pieces of sensor energy data and PCI bus energy data are stored in real time using a large-capacity disk array composed of multiple SATA hard disks. ,e function and performance of the energy data acquisition and storage system were tested. After the actual system test, the experimental results show that the transmission speed of the system through the PCI bus exceeds 200 MB/s, the writing speed of the continuous disk array is 240 MB/s, and the real-time acquisition and recording speed is 100 MB/ss. Conclusion. ,e system effectively solves the problems of high-speed data acquisition and storage and large capacity data transmission of key sensor nodes. energy data. With the increase of the amount of energy data 1. Introduction to be tested and the types of test energy data, it is necessary to In the research of aerospace, geological exploration, satellite collect and store multiple energy data signals at the same navigation, and other fields, it is necessary to collect and time, which puts forward higher requirements for the record some important energy data parameters for energy performance of the energy data acquisition and storage data analysis and research, which has important reference system. Because FPGA can process a large amount of parallel value for the next experiment improvement and result data at the same time, the current mainstream data acqui- analysis and is also more important for the result analysis of sition memory design schemes use FPGA as the control scientific research energy data. ,erefore, the research and module, write logic circuit programs in FPGA to control, design of energy data acquisition memory is of great sig- receive the data signals sent from the outside, and save them nificance for these fields [1]. ,e main application of data in the memory. In recent years, with the rapid development acquisition memory in these fields is to collect and record of semiconductor technology and the maturity of produc- the data collected by various sensors during the working tion technology, energy data acquisition memory has ush- process of aircraft, such as vibration signal, noise signal, ered in new development. As the main control module of image signal, and other key data. ,ese energy data play a energy data acquisition memory, large-scale integrated key role in the monitoring of aircraft operation status, fault circuits such as PGA and single chip microcomputer make analysis, environmental energy data acquisition, and so energy data acquisition and storage more complex and forth; it is very important to accurately collect and record functional by software programming. ,e products 2 International Transactions on Electrical Energy Systems developed in recent years have made great progress in 3. Research Methods multichannel energy data acquisition, large-capacity storage, 3.1. Main Functions and Technical Indicators. In the mea- high-speed storage, and so forth [2]. surement system, in order to accurately measure the jitter of ,erefore, it is of great significance to improve the the flexible baseline and the change of the relative attitude of collection and storage of real-time energy data by using the two antennas in real time, it is necessary to select a CCD emerging technologies. camera with high frame rate and large array and a high- precision laser rangefinder for combined measurement, 2. Literature Review which will produce a large amount of high-speed image energy data and distance energy data output by the laser For real-time energy data collection and storage, Miao rangefinder [8]. ,erefore, the main function of the high- et al. proposed realizing feeder automation FA by building speed acquisition and storage system designed in this paper distribution automation system (DAS) [3]. ,e meaning is to control the time synchronization between the mea- of feeder automation is to monitor the status of current, surement sensors, complete the real-time energy data ac- voltage, interconnection switch, and section switch on the quisition of each sensor, and shunt the collected energy data. feeder remotely. Yarlagadda et al. proposed updating the One channel of energy data is stored at high speed; another solid-state storage technology in the aerospace energy channel of energy data is output to another real-time pro- data storage system, changed the previous method of cessing system. According to the requirements of flexible using tape storage, and improved the stability and reli- baseline measurement system, the system in this paper ability of the energy data storage technology [4]. Kumar should be able to collect and store the measurement energy et al. proposed the integration of FPGA technology and data of two sensors in real time. ,e technical indicators to ASIC technology, so as to reduce its disadvantages of large be achieved mainly include continuous acquisition speed, volume, insufficient capacity, and larger power con- continuous storage speed, and minimum storage capacity. sumption than ASIC and then optimize energy data ,e CCD camera in the system adopts a high-resolution, transmission [5]. He et al. proposed that FPGA chip is the high frame rate area array digital camera, the image reso- core device, and online driving fatigue detection can be lution is 1608 columns ×1208 rows, and the maximum frame realized only by matching with appropriate digital image rate of the camera is 30 Hz. ,e AD sampling of the camera algorithm. ,e design omits the DSP control chip and energy data is 10 bits, and the energy data acquisition is only expands the memory to form a simplified minimum 8 bits high, so the energy data volume generated by the CCD system. Reprogrammable features and highly integrated camera per second is about 55.57 MB [9]. LRFS-0040-2 laser features can greatly reduce the design cycle and design rangefinder is used as the laser rangefinder. ,e measure- cost [6]. Tappari proposed designing the internal logic ment rate can reach 50 Hz at most. RS422 interface is used as circuit of FPGA and creating the firmware program of the energy data interface, and the amount of energy data FX3. It realizes the receiving and storage of LVDS energy generated is 9.6 kB/s. ,e energy data volume of the two data and the reading of energy data in memory by sensors per second is about 56 MB/s, so the continuous computer [7]. Kowalczyk et al. proposed using multiple acquisition speed of the acquisition system must be greater hard disks to form a RAID array (cheap redundant disk than 56 MB/s before real-time energy data acquisition of the array). High-end storage functions and redundant energy two sensors can be carried out. Only when the continuous data security were provided for large servers. Raid storage rate is greater than the acquisition speed can the combines multiple independent hard disks (physical hard energy data be stored in real time and accurately. ,erefore, disks) in different ways to form a hard disk group (logical the continuous storage speed should be greater than 56 MB/ hard disk), thus providing higher storage performance s, and the maximum theoretical read-write speed of SATA than a single hard disk and providing energy data re- hard disk can reach 150 MB/s. Using multiple SATA hard dundancy technology. disks to form a RAID array can provide higher storage According to the requirement of real-time energy data performance than a single hard disk. According to the re- acquisition and storage of key sensor nodes, this paper quirements of the flexible baseline measurement system, the proposes a solution of real-time energy data acquisition and longest continuous working time of the acquisition storage high-speed storage based on FPGA and designs and im- system is about 2 h, and the minimum storage capacity plements the key hardware functions. ,e system uses FPGA required is about 390.76 GB [10]. According to the demand for core logic control, synchronously collects and controls analysis of the above energy data acquisition system and the energy data of CCD camera and laser rangefinder, sorts considering the scalability of the system and the needs of out and uses external large capacity SDRAM group for actual energy data transmission and terminal processing, it is cache, uses a special PCI interface chip PLX9656, realizes the required that the energy data acquisition and recording high-speed transmission of two pieces of sensor energy data speed should reach 70 MB/s, the continuous disk array and PCI bus energy data, and uses a large capacity disk array writing speed should reach 120 MB/s, and the storage ca- composed of multiple SATA hard disks for real-time storage. pacity should reach 2 TB. For the 32-bit/33 MHz PCI bus, it ,e function and performance of the energy data acquisition can generally reach 80 MB/s in actual use. ,e energy data in and storage system are tested to prove the real time, stability, and out of the system memory must pass through the PCI and efficiency of the real-time energy data acquisition and bus, which will reduce the efficiency of the bus by half. ,e storage of key nodes. International Transactions on Electrical Energy Systems 3 communication interface between PCI bus and external bus acquisition speed of the system must be greater than 56 MB/ s, so the 64-bit/66 MHz PCI bus is selected, and the peak to realize the communication between them. In this system, PLX9656 is used to design high-speed PCI card to realize the speed of energy data transmission can reach 528 MB/s. ,e existing system shows that the actual transmission speed of functions of setting camera parameters, setting laser ranging the 64-bit/66 MHz PCI bus can reach more than 200 MB/s, parameters, setting sampling parameters, reading image so the transmission speed of the PCI bus fully meets the energy data, and so on. PLX9656 is the PCI interface system requirements [11]. controller with the highest performance at present. It has the ,e whole system is mainly composed of CCD camera, performance of 66 MHz and 64 bits at PCI end and 66 MHz laser rangefinder, PCI energy data acquisition card, SATA and 32 bits at local end and conforms to PCIV2.2 specifi- cation. ,e key point of PCI interface design in this system is disk array, and computer. ,e PCI image acquisition card is mainly composed of sensor energy data interface, FPGA the setting and implementation of PLX9656 local bus working mode and energy data transmission mode. ,e local logic control chip, cache, and PCI interface chip. ,e principle of the scheme is as follows: Firstly, the host sends bus of PLX9656 can be set to three modes: M mode, C mode, and J mode. According to the characteristics of the system, C commands to configure the CCD camera and laser range- finder. After the configuration is completed, the acquisition mode can be selected, and the working mode of C mode can is started. ,e high-speed image energy data output by the be realized by pulling down the pins of mode1 and mode0. In CCD camera and the synchronous control signal are sent to C mode, the energy data transmission mode is divided into the FPGA and cached in the FPGA. ,e energy data of the master mode operation, slave mode operation, and DMA laser rangefinder is also sent to the dual-port RAM of the operation. ,e DMA working mode can realize the fast FPGA through the serial port for caching. After the FIFO is transmission between high-level peripherals and memory without CPU intervention, so it is more suitable for the half full, the energy data of the CCD camera and the laser rangefinder are shunted under the control of the FPGA, one transmission of CCD camera energy data and laser range- finder energy data. ,e DMA transmission mode can be of which is sent to the external SDRAM group for caching. After the SDRAM is stored in the set image frame number, it realized by setting dmamode0/1 and PCICR of the internal registers of PLX9656 [13]. is sent to the PCI for interruption. ,e host responds to the interruption, reads the data from the SDRAM to the memory for processing, and writes the data to the hard disk 3.3. FPGA Core Logic Control to complete real-time storage. ,e other way is sent to the relevant real-time processing system for processing. ,e 3.3.1. Sensor Trigger Setting. In this design, the working block diagram of the whole design scheme is shown in modes of the two sensors are set through the host terminal, Figure 1. the mode setting string is transmitted to the FPGA through ,e design of data real-time acquisition and storage the PCI bus, and the communication with the camera and system applied to flexible baseline measurement system the laser rangefinder is realized through the serial port includes the following key technologies: CameraLink in- controller, so as to complete the configuration of the camera terface technology, multisensor synchronization technology, and the laser rangefinder. After the camera and the laser real-time acquisition and cache of multisensor data, and rangefinder receive the configuration command, the re- real-time storage of multisensor data. sponse information is also transmitted to the FPGA through the serial port controller and then transmitted to the host through the PCI bus. In order to realize the synchronous 3.2. Key Design and Implementation of Real-Time Energy Data control with the laser rangefinder, the camera selects the Acquisition and Storage System. ,e experimental camera software external trigger mode. In this mode, an EXSYNC adopts CameraLink standard interface, and the basic con- trigger signal with a frequency of 20 Hz needs to be gen- figuration adopts standard MDR26 connector output. ,e erated in the FPGA and sent to the CCD camera for ex- system uses FPGA as the main control chip of the acquisition posure reading energy data. ,e low-level width of EXSYNC card, and the i/o standard supported by FPGA is LVCMOS/ is 10 us, and the exposure time of the camera is set by the LVTTL signal [12]. ,e main function of DS90CR288A is to host terminal. complete the conversion from LVDS to TTL level signals and the conversion of serial signals into parallel signals. In order to set parameters and trigger control of the camera, it 3.3.2. Energy Data Synchronization Control. ,e EXSYNC is necessary to convert the camera control signals trigger signal is sent to the laser rangefinder and camera at (CC1–CC4) and signal SerTC (serial to camera) output from the same time to realize the output synchronization of the FPGA into LVDS signals through level conversion chip two sensors. Because the measurement speeds of the two ds90lv047 and send them to the receiver. In order to receive sensors are different, the output frame rate of the camera is the response signal (SerTFGserial-to-frame-grabber) sent by 20 frames/s, and the output frequency of the laser range- the camera to the acquisition card, ds90lv048 is used to finder is 50 Hz, so the key to the design of data synchro- convert the LVDS signal into TTL signal, which is sent to nization is how to record the single frame image data and the FPGA and sent to the host for display. laser rangefinder data at the same time. ,e timing diagram ,e system adopts 64-bit/66 MHz PCI bus to realize of the synchronous acquisition of the two sensors is shown high-speed energy data transmission. PCI interface is the in Figure 2(a). Clk100 Hz is the least common multiple of 4 International Transactions on Electrical Energy Systems SDRAM SDRAM 32M*32bit 32M*32bit SDRAM control interface PCI-X bus Write to Read FIFO FIFO PCI Cable RS422 signal Host UART Laser DB9 Interface receive/transmit DPRAM PCI Ranging interface chip interface interface RAID card controller Camera Interface DPRAM Latch FIFO link chip 1/2 SATA disk array FPGA Figure 1: Design scheme block diagram of real-time energy data acquisition and storage system. 0 0 02468 10 02468 10 Time us Time us Sensor 2 collects the timing data Sensor 1 Simulation data Sensor 1 collects the timing data Sensor 2 Simulation data (a) (b) Figure 2: Synchronous acquisition design and simulation sequence diagram of CCD camera and laser rangefinder. (a) Collect energy data. (b) Simulation energy data. simulation sequence diagram is shown in Figure 2(b) [15]. two frequencies, which can be set according to the internal resource usage of FPGA. energy data_lrf_sel is the selected According to the simulation results in Figure 2, the syn- laser energy data, where I indicates that the energy data at chronization design scheme in this paper can effectively this time is invalid, and V indicates that the energy data at reduce the delay between the two sensors and collect the this time is valid [14]. ,e energy data synchronization relative synchronization energy data of the two sensors. scheme is that after the camera energy data enters the FPGA, Although it is not strictly synchronous, it can meet the it is sorted and cached in two dual-port RAM, and the laser requirements of the flexible baseline measurement system. rangefinder sends the energy data into the FPGA through the serial port receiver. ,e serial port receiver of this design 3.3.3. Energy Data Caching and Collation. ,e caching scheme adopted in this system is to firstly latch the image has FIFO cache, and the energy data is sent to the dual-port RAM for further cache after caching. ,e write enable Wen energy data and control signal at three levels, because the image energy data output by the experimental camera is the signal of the dual-port RAM is generated according to the timing diagram shown in Figure 2(a), and the laser energy energy data of two taps, and the energy data of the two taps data is written at this time into the dual-port RAM when the are, respectively, sent to the two dual-port RAM inside the Wen signal is valid. When the read enable signal is valid, first FPGA for caching. ,e energy data of the left tap is stored the laser rangefinder energy data in the dual-port RAM is according to the sequential address, and the energy data of read into FIFO, and then the image energy data of the the right tap is stored according to the reverse address, so as corresponding frame is read into FIFO. After the FIFO is half to splice the energy data of the two taps into a complete full, the laser rangefinder energy data and camera energy image. When the enable signal is valid, the data of the two data are sent to the external SDRAM for further caching. ,e dual-port RAM is sent to FIFO for further caching. When Time sequence data Time sequence simulation data International Transactions on Electrical Energy Systems 5 disks with a capacity of 1 TB, which are configured into raid0 the FIFO data is half full, the FIFO data is sent to the external SDRAM memory through the SDRAM interface controller. mode through raid card to maximize disk access rate and form a high-speed and large capacity storage device. ,e design block diagram of the entire digital camera energy data 3.3.4. PCI Logical Interface. ,e system completes the acquisition and storage device is shown in Figure 4. ,e communication between FPGA and PLX9656 through PCI system uses the interface chip PLX9656 to send the energy local logic interface. After the system is powered on, the data output from the real-time acquisition module to the internal register of PLX9656 is reset by the RST\\\. At the system memory through the PCI bus and then writes the same time, PLX9656 outputs local reset signal LRESET and energy data in the memory into the SATA hard disk array checks whether EEPROM exists [16]. If the local DMA mode through the PCI bus under the control of the raid card. ,e is used for control, the whole handshake process is as fol- theoretical continuous disk writing speed can reach more lows: First, when the energy data in the SDRAM cache than 400 MB/s [22]. reaches the set value, the signal is valid, and the PLX9656 sends an interrupt request signal to the host. If the CPU 4. Result Analysis responds to the interrupt, it will issue the DMA read command, the number of bytes to be read, and the address In the experiment, the function and performance of the information in the corresponding program of the interrupt. system are tested, respectively. Performance test mainly PLX9656 applies for the local bus to make the LHOLD signal includes real-time acquisition and recording speed test, valid. Once again, the FPGA effective ready\\r\m signal is continuous disk array writing speed test, and stability test. enabled, and the SDRAM control interface read enable ef- For the function test of the system, the simulation image and fective signal is enabled, and the energy data begins to appear the actual image energy data acquisition test are carried out, on the LD energy data bus. When the last byte of energy data respectively. ,e analog image is the energy data with starts to be transmitted, the PLX9656 drives the blast\\ signal regular circulation generated in FPGA, and the corre- to be valid, and the FPGA has no ready\ signal [17]. Finally, sponding image is the stripe image. ,e function of the the SDRAM read enable signal is made invalid, PLX9656 acquisition system is verified according to whether the drives LHOLD to be invalid, the local bus is released, and collected energy data is correct. ,en switch to the actual then FPGA also drives LHOLDA to be invalid, ending the energy data source and collect the moving image of the primary energy data transmission. ,e design of DMA cooperative target. ,e test results of simulated and mea- transmission is shown in Figure 3. sured image energy data show that the system can collect and store energy data correctly without image dislocation, which 3.4. Cache Design and Real-Time Cache Design. Because the verifies the correctness of the system function. internal cache capacity of PCI interface chip is too small, the ,e test method for the real-time acquisition and re- cache must be used to cache the energy data in the process of cording speed of the system is as follows: because the output real-time collection and then sent to the host through PCI frequency of the sensor in the system is limited, it cannot bus to improve the transmission speed and performance of reflect the maximum acquisition and recording speed of the the system [18]. Large-capacity and high-speed SDRAM is system. Analog images of different frequencies are generated easy to buy and the price is moderate. ,e system uses in FPGA, real-time acquisition and disk writing are carried SDRAM for caching. Windows is a multithreaded and out through the system, and the image is played back by the preemptive operating system. In order to reduce the in- upper computer software to check whether there is frame terruption of threads due to the end of CPU occupation loss and dislocation. ,e measured results show that when time, the interruption interval should be greater than the the output frequency exceeds 50 Hz, if only the image is maximum thread execution time of 20 ms, so the cache collected and not saved, the image acquisition is correct, but capacity should be at least 20 ms × 70 MB/s × 2 � 2.8 MB. ,e when the disk is saved at the same time, the image dislo- caching scheme adopted by the system is to connect 2 groups cation and frame loss begin to occur. ,ere are two main of 32 m∗ 32-bit SDRAM to FPGA, which is configured by 4 reasons: One is that when the frequency is greater than 50 Hz pieces of SDRAM, and is used for energy data buffering from and the amount of energy data is greater than 100 MB/s, the camera to PCI. ,e SDRAM is encapsulated into the FIFO theoretical reading and writing speed of the external cache of interface through the controller, the camera energy data is the system is 133 MHz. Because the FIFO interface is made written into the FIFO, the interrupt is sent to PCI according to read while writing, the transmission speed is halved, to the set number of images, and then the camera energy which may lead to the cache energy data not being read in data is read by PCI, thus overcoming the shortcomings of time, resulting in image dislocation and loss. ,e other is complex SDRAM structure and difficult switching control that the read and write of the system in the host memory is a circuit [19, 20]. thread, which reads and writes energy data at the same time, Real-time streaming disk has always been the biggest resulting in the rate falling behind. To sum up, the acqui- bottleneck of high-speed energy data acquisition technology, sition and recording speed of the system can reach 100 MB/s, which directly restricts the real-time storage capacity of meeting the index requirements of 70 MB/s. acquisition and storage devices [21]. ,e system adopts PCI- ,e speed test method of continuous writing disk array is X bus motherboard supporting 66 MHz, 100 MHz, and to use a special hard disk read-write speed test software to 133 MHz/64 bits. It consists of 8 high-speed SATA hard write energy data of different capacities from the host 6 International Transactions on Electrical Energy Systems Send the Up FIFO engine PCI The DMA controls Interrupt Express the status register control Core Receive the Down FIFO engine Figure 3: DMA transmission design. Real-time storage module Data storage interface SATA disk Array PC storage PCI - X bus The data source The CCD camera Laser rangefinder Real-time acquisition module Data acquisition and cache module Camera and laser rangefinder control module Figure 4: Design of real-time high-speed storage scheme. Table 1: System stability test results. Working hours (h) 2 2 4 4 6 6 Software external Operating mode Free running Software external trigger Free running Software external trigger Free running trigger Frame loss rate (%) 0 0 0 0 0.03 0.01 memory to the disk array and average the speed of software frame loss rate of the system. ,e actual test results are statistics. ,e measured results show that the real-time shown in Table 1. It can be seen from Table 1 that, within the storage speed of the system can reach more than 240 MB/s in required working time of the system, the system has no different acquisition times, meeting the requirements of the frame loss under different modes, and the performance is very stable. Even if the working time is 3 times the required system index of 120 MB/s. In addition, the system uses 8 1 TB SATA hard disks, with a total recording capacity of time, the maximum frame loss rate of the system is only 8 TB, which meets the index requirement of 2 TB minimum 0.03%, which can meet the requirements of the measure- recording capacity of the system. ment system. ,e stability test method of the system is as follows: under different working modes, collect the energy data of 5. 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International Transactions on Electrical Energy SystemsHindawi Publishing Corporation

Published: Aug 23, 2022

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