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Controller Design Considerations for ACM APFC Systems

Controller Design Considerations for ACM APFC Systems Hindawi Publishing Corporation Advances in Power Electronics Volume 2012, Article ID 286861, 9 pages doi:10.1155/2012/286861 Research Article Alexander Abramovitz Department of Electrical Engineering and Computer Science, University of California, Irvine, CA 92697, USA Correspondence should be addressed to Alexander Abramovitz, alabr@hotmail.com Received 27 February 2012; Revised 6 August 2012; Accepted 7 August 2012 Academic Editor: C. M. Liaw Copyright © 2012 Alexander Abramovitz. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited. This paper is concerned with performance of the current shaping network in Average Current Mode (ACM) Active Power Factor Correction (APFC) systems. Theoretical expressions for the ripple components are derived. Then, ripple interaction and impact on the current loop reference signal are investigated. A modification of the controller network is suggested that results in an improved Total Harmonic Distortion (THD). Design guidelines are suggested. The theoretical predictions were validated by simulation. 1. Introduction of the implementation, however, the duty cycle program- ming is implemented according to the converters input port Over the past few years, a variety of current shaping method- ideal average relationships and ideal modulator ramp signal. ologiesweredeveloped forActivePower Factor Correction As a result, accurate current loop operation can only be (APFC) [1–3]. Each approach undertaken is a compromise in attained in the Continuous Conduction Mode (CCM) under between the performance indexes and the circuit complexity negligible current ripple conditions. In practice, however, andcost. TheCriticalConductionMode(CrCM)APFC the CCM-DCM mode changes, current ripple, and ramp operating on the CCM-DCM boundary [4–7] shapes the carrier imperfections cause the duty cycle to deviate from the average input current by comparator/zero detector and ideal relationship resulting in distortion in the average input is unconditionally stable. However, the natural simplicity, current. robustness, and stability of CrCM APFC are offset by The very proper average current mode three-loop APFC high ripple current which cause increased conduction and [15–18] achieves its control objectives by a control scheme core losses. Difficulties in filtering the variable frequency shown at Figure 1. The three-loop APFC uses a slow outer current ripple and poor efficiency restrict this technique to voltage loop to control the output voltage and a fast current low-power and low-cost applications. Other Discontinuous loop for active shaping of the average input current. The Conduction Mode (DCM) based designs, which upside is reference signal for the inner current loop is derived from the simplicity suffer from similar problems exhibiting also higher rectified power line voltage by the multiplier-squarer-divider harmonic distortion of the line current [8, 9]. circuit. Additional outer feed-forward loop compensates for APFC without line voltage sensing, [10–13] stands out as the line voltage variations. Such an APFC could be designed a robust, technologically simple, and cost-effective solution. to operate in CCM most of the cycle but could tolerate also A simple and clear physical insight into the principle of DCM intervals sustaining good current tracking. operation of the current loop of this class of APFCs was The two feedback loops of the APFC of Figure 1 have suggested in [14]. All of the mentioned above APFCs with conflicting objectives. In particular, a strong outer loop that no input voltage sensing make use of a hidden current loop manages to stabilize the output voltage will deteriorate the inside a DC-DC converter. The designs mainly differ in their power factor by dictating an input current that ensures method of realization of the transresistive feedback, PWM, a fixed output voltage rather than the desired sinusoidal- and supplementary current loop control circuitry. Regardless shaped current. The outer loop is usually designed with 2 Advances in Power Electronics L V D I o ch AC v (θ) out i (θ) v in AC CA PWM cp v v d e − DIV VA MULT + V ref ff SQR LPF Figure 1: Three-loop ACM APFC system block diagram. a limited bandwidth as well as with a low gain so to distortion components, which originate in the outer loops. heavily attenuate the output ripple. Otherwise, the ripple will Based on the results, the requirements for maintaining distort the input current by penetrating into the reference a distortion-free current reference are formulated. Finally, of the current loop. As a result the response of the outer under the assumption of the ideal current loop, the residual loop to load variations is rather slow. The outer loop error distortion caused by the proposed ripple cancellation scheme amplifier output voltage contains a second harmonic ripple is examined. component which modulates the current amplitude and thus distorts the current reference signal. Obviously, this also 3. General Considerations: Review of results in distorted line current. APFC Output Current and Voltage This paper suggests that one of the causes of the major current distortion in most, if not all, APFC systems is the sec- Under the assumptions above, the line voltage and current of ond harmonic ripple components that are brought into the the APFC of Figure 1 are in phase and of a sinusoidal shape. current reference by the outer loops. The proposed solution To simplify the notation the analyses are confined to one- to the problem can be found by compensating the output half of the line period for which the rectified inputs can be ripple rather than filtering. This alternative was investigated expressed as in this study analytically and by simulation. It was found that such a strategy is possible and furthermore it can easily be v (θ) = V sin θ, in m implemented by simple additional circuitry to commercially (1) i (θ) = I sin θ, in m available APFC controllers. This paper presents the theory of the proposed approach and demonstrates the improvement where θ = ωt is the power line angle (0 ≤ θ ≤ π). The ins- in Total Harmonic Distortion (THD) that can be gained and tantaneous input power of the APFC is given by provides design guidelines. p (θ) = v (θ)i (θ) = V I sin θ = P (1 − cos 2θ), in in in m m av (2) 2. Basic Assumptions and Strategy where P = (1/2)V I is the average power over the power av m m The analyses to follow are carried under the following assum- line cycle. The instantaneous charging power at the output of ptions: the APFC is a function of the output voltage, v (θ), and the out (a) the line voltage is a pure sinusoidal wave; output charging current, i (θ): ch (b) the rectifiers are ideal; p (θ) = v (θ)i (θ) ≈ V i (θ). out out ch DC ch (3) (c) the power stage is linear and 100% efficient; Here, the output ripple is neglected, that is, the output (d) the current loop is ideal, that is, it forces the input voltage, v (θ), of the APFC is assumed to be equal to its out current to follow the reference signal; average value, V . For an ideal power stage with 100% DC (e) the holdup capacitor is large and hence the output efficiency, instantaneous input and output power are equal: ripple is small as compared to the dc output voltage. p (θ) = p (θ). (4) in out The following approach is adopted: initially it is assumed Applying (2)–(4), the charging current, i (θ), is approxi- ch that the input current is a pure sine wave. Next, the outer mated to loop ripple components propagation mechanism into the current reference circuit is investigated. The assumption of av i (θ) = (1 − cos 2θ). (5) ch the ideal current loop helps identify the current reference DC Load Advances in Power Electronics 3 Figure 2: Simulation diagram of the modified three-loop APFC based on the behavioral model. The holding capacitor current, i (θ), is the difference bet- where V = (2/π)V , V = −(4/3π)V , V = c i0 m i2 m i4 ween the charging current and the DC load currents: −(4/15π)V , and so forth are the Fourier coefficients. The relative phases of the harmonics are zero. When this av i (θ) = i (θ) − I = − cos 2θ. (6) signal is fed to the LPF feed-forward network of Figure 2, c ch DC DC the LPF output voltage, v (θ), appears as The AC current of the holdup capacitor, i (θ), generates a second harmonics ripple component, v (θ), which appears o2 v (θ) = V H + V H cos 2θ + φ f i0 f 0 i2 f 2 f 2 at the output: (12) + V H cos 4θ + φ +··· , 1 −P i4 f 4 f 4 av v (θ) = i (θ)dθ = sin 2θ. o2 c (7) ωC 2ωCV DC where H and φ are the gain and phase of the LPF transfer f n f n Clearly, the output ripple is a linear function of power. The function at the nth harmonic of the line frequency. Since the instantaneous output voltage including the second harmonic amplitude of the harmonics of the rectified voltage decreases ripple can now be written as with their frequency and since the LPF provides sufficient attenuation at high frequencies, harmonic components v (θ) = V + v (θ). (8) out DC o2 higher than the second one may be neglected at the output of Using (7) yields the LPF. Therefore, the response of the LPF is approximated to av v (θ) = V 1 − sin 2θ . (9) out DC 2ωCV DC V i2 f 2 v (θ) = V H 1+ cos 2θ + φ . (13) f i0 f 0 f 2 V H The second harmonic frequency peak-to-peak ripple, γ,is i0 f 0 derived from the above to be The v (θ) signal is squared with the gain of k by the squarer f s ΔV out P pp av γ = 100% = 100%. (10) circuit, see Figure 1. Applying the same reasoning as above V ωCV DC DC the resulting quadratic term could be neglected. Therefore, the approximated feed-forward signal is 4. The Feed-Forward Path Signal ( ) v θ ff The rectified input voltage fed to the feed-forward path filter (LPF) of the PFC topology under study, see Figure 1,can be V f 2 i2 2 2 2 = k v (θ) ≈ k V H 1+2 cos 2θ + φ . represented by the Fourier series: s s f 2 f i0 f 0 V H i0 f 0 v (θ) = V + V cos 2θ + V cos 4θ +··· , (11) in i0 i2 i4 (14) 4 Advances in Power Electronics Substituting the values of the Fourier coefficients, the expres- The second harmonic component, v (θ), appears as the res- e2 sion for the feed-forward signal fed to the divider is obtained ponse of the error amplifier to the output voltage ripple, as v (θ), given by (7) o2 H P v2 av v (θ) = V v (θ), (15) ff ff 0 ff n v (θ) = − sin 2θ + φ . (22) e2 v2 2ωC V DC 2 2 2 where the term, V = k (4/π )V H and v (θ) is the ff 0 s ff n m f 0 Here, the error amplifier’s gain and phase, at the frequency of normalized feed-forward voltage: the second harmonic, are denoted H and φ respectively. v2 v2 Combining (20), (21), and (22), yields the expression for the v (θ) H ff 4 f 2 error amplifier output voltage delivered to the input of the v (θ) = = 1 − cos 2θ + φ . ff n f 2 (16) V 3 H ff 0 f 0 divider as Equation (15) describes a waveform having a DC value v (θ) = V v (θ), (23) e e0 en proportional to the square of the amplitude of the input where v (θ) is the normalized feedback voltage: en voltage, V , scaled by the DC gain of the feed-forward 2 2 v K H path: k (4/π )H . The normalized feed-forward signal e(θ) v2 f 0 v (θ) = = 1 − sin 2θ + φ . (24) en v2 V 4V ωC (16) contains an undesirable second harmonic component e0 DC propagating into the current reference. Interesting to note Note that the normalized second harmonic ripple compo- is that the normalized ripple (16) at the output of the nent at the output of the error amplifier is constant and inde- LPF is constant and depends on the attenuation at the pendent of the power level output voltage of the APFC. This second harmonic frequency, (4/3)(H /H ). The amount f 2 f 0 observation forms the basis for the following development of of attenuation is determined by LPF configuration and its the proposed ripple cancellation method. comer frequency. Lowering the corner frequency increases the attenuation, lowering also the harmonic contents of the 6. The Current Programming Signal feed-forward signal. This results in better line current quality. However, lowering the corner frequency slows the APFC To produce the correct current programming signal, the response to line variations. APFC circuit of Figure 1 uses the divider output, v (θ), to modulate the line voltage waveform. The divider output sig- 5. The Voltage Feedback Path Signal nal is calculated using (15)and (23) yielding ⎛ ⎞ To establish the operating point of the voltage error amplifier v (θ) π k P e d av ⎝ ⎠ v (θ) = k = v (θ). (25) d d dn the issue of the input current generation should be addressed v (θ) 2 k KH V ff s f 0 first. The input current of the PFC circuit of Figure 1 is gen- Here, k is the divider gain constant and v (θ) is the nor- erated by the following algorithm: d dn malized divider output: 1 − (K/4V )(H /ωC) sin 2θ + φ i (θ) = I sin θ = K(v (θ)) (V sin θ). (17) v (θ) in m e m en DC v2 v2 V v (θ) = = . dn v (θ) ff n 1 − (4/3) H /H cos 2θ + φ f 2 f 0 f 2 where, v (θ) is the voltage feedback error amplifier signal and (26) K is the system’s gain constant. Thus the amplitude of the The current programming signal, v (θ), produced by mod- cp input current and the average input power are ulation of the line voltage (1) with the divider output (25)is v (θ) given by I = K , (18) v (θ) = k v (θ)v (θ) cp m d in I V K ⎛ ⎞ m m P = = v (θ). (19) av e (27) π k k 1 P 2 2 m d av ⎝ ⎠ = v (θ) sin(θ), dn 2 k KH V s m f 0 The advantage of the feed-forward path is apparent; the APFC power level (19) is independent of the line voltage. where k is the multiplier gain constant. The current pro- The steady-state output voltage of the error amplifier, gramming signal amplitude is therefore v (θ), contains the DC term, V , as well as the second har- e e0 ⎛ ⎞ monics ripple component, v (θ): π k k 1 P e2 m d av ⎝ ⎠ v = v (θ). (28) cpm dn 2 k KH V s m f 0 v (θ) = V + v (θ). (20) e e0 e2 Equations (27)and (28) reveal the mechanism by which The steady state DC error amplifier voltage, V ,requiredto e0 distortion components of the outer loops are introduced into maintain the average power level, P , could be derived from av the current reference. The term v (θ) contains harmonic dn (19) neglecting the ripple component as components which modulates the current programming signal amplitude (28). Consequently, the input current of the (21) V = P . e0 av APFC could not possibly be any less distorted than (27). K Advances in Power Electronics 5 v (θ) in v (θ) in R R si sf R ff2 ff1 R 100 k 100 k ff1 ff2 v (θ) 910 k 91 k f 910 k 91 k v (θ) R 150 k C C ff3 ff1 ff2 C C ff2 ff1 R C ff3 s 20 k 0.1 μF 0.47 μF 0.1 μF 0.2 μF 20 k 0.1 μF (a) (b) out C 80 nF vf (6.5 nF) vi R 177 k vf 510 k (200 k) (910 k) vd ref 9.76 k 7.5 V (17.4 k) (c) Figure 3: APFC feed-forward filters: original design (a); modified (b); voltage error amplifier configuration with original and modified (in brackets) values (c). 7. The Power Gain Constant for the following reasons. To ensure stability and adequate phase margin, the error amplifier usually has a single-pole When the current loop tightly regulates the input current, the transfer function of −20 db/decade gain roll off beyond its output voltage of the current sensing network, v (θ), see sense corner frequency and its filtering action is poor. Since the Figure 1, is forced to follow the current programming signal, ripple frequency is quite low the bandwidth of the error v (θ): cp amplifier is severely restricted resulting in poor transient response. A high-order low-pass filter may be used to achieve v (θ) = v (θ). sense cp (29) efficient filtering of the average component of the rectified input voltage. However, once again due to the low second In the most common case, the current sensing network is just harmonic frequency the filter has a narrow bandwidth and a series resistance, R , so the amplitude of the sensed voltage its transient response is rather poor. Here an alternative is approach is proposed. Equations (27)and (28) suggest that av it is possible to achieve distortion-free current programming V = I R = 2 R . (30) sense m s s V signal by making the normalized divider output (26)equal unity: The power gain constant K may be found substituting (28), (30) into (29) and assuming an ideal v (θ), that is, (26) dn 1 − (K/4V )(H /ωC) sin 2θ + φ DC v2 v2 equals unity. This gives v (θ) = = 1. dn (32) 1 − (4/3) H /H cos 2θ + φ f 2 f 0 f 2 π k k 1 m d K = . (31) 4 k R H s s f 0 To satisfy (32) requires that the normalized ripple compo- nents of the error and the feed-forward signals be equal both This relationship remains valid also for the general case, in amplitude and phase: when the current sensing network transfer function low fre- quency gain is denoted by R . K H 4 f 2 v2 sin 2θ + φ = cos 2θ + φ . (33) v2 f 2 4V ωC 3 H DC f 0 8. Filter Design for Minimum Line Current Distortion Since the normalized ripple components are of the same frequency and of a constant amplitude, it is possible to fulfill Examination of (27)and (28) reveals that any harmonic (34) by proper controller circuit design. For this purpose disturbances at the divider output will produce cross prod- both amplitude and phase conditions must be satisfied. The ucts with the sine term. This will appear as harmonics in amplitude condition defines the LPF attenuation needed to the current programming signal and cause distortion in the equate the amplitudes of the ripple components: input current. Traditionally, the designers [15–18] minimize the distortion by providing large attenuation of the second 3K H harmonic, that is, minimizing the H and H terms in f 2 v2 v2 f 2 = . (34) (16), (24), and (26). However, this has only a limited success H 8V (2ω)C f 0 DC 6 Advances in Power Electronics 1.04 1.08 dn 1.02 1.04 dn en ffn 0.98 0.96 en ffn 0.96 0.92 335 336 338 340 342 344 346 348 325.9 328 332 336 340 344 347 Time (ms) Time (ms) V(div)/1.18 V(sqr)/3.7345 V(e)/4.412 V(e)/4.824 V(sqr)/3.7424 V(div)/1.29 (a) (b) 1.08 1.04 dn ffn 0.96 en 0.92 326 328 332 336 340 344 347 Time (ms) V(sqr)/3.735 V(e)/2.5356 V(div)/0.678 (c) i norm line norm line norm i norm 0.5 ch norm SEL≫ −2 0 200 202 204 206 208 210 212 214 216 200 202 204 206 208 210 212 214 216 Time (ms) Time (ms) V(rec)/155 V(out)/400 V(line)/155 I (V )/6.6382 rs I (G )/2.562 −I(Vline)/6.6382 2 (d) Figure 4: Normalized voltages of the error amplifier v , the feed-forward network v , and the divider output v , in the original design en ff n dn (250 W) (a); modified design (250 W) (b), Modified design (125 W) (c), Modified design waveforms of the normalized rectified voltage V , in converter’s input current I , and the APFC’s charging current I (d). in ch This could be rearranged using (31) into the following form: The phase condition could be derived by equating the sine and cosine terms in (33) and using elementary trigo- nometry relationship: 3π k k m d H = H , f 2 v2 (35) 128fCR H V k s f 0 DC s cos 2θ + φ = sin 2θ + φ = cos 2θ + φ − . (36) f 2 v2 v2 where, f is the line frequency. (V) (V) (V) Advances in Power Electronics 7 Table 1: Analysis printout of the original circuit, full power (250 W). Fourier components of transient response DC component = 2.758333E − 04 Harm no. Freq (Hz) Fourier comp Normalized comp Phase (Deg) Norm. phase (Deg) 16.000E +01 3.198E +00 1.000E +00 −1.797E +02 0.000E +00 21.200E +02 4.295E − 04 1.343E − 04 1.456E +02 5.050E +02 31.800E +02 5.949E − 02 1.860E − 02 1.742E +01 5.565E +02 42.400E +02 1.831E − 04 5.724E − 05 −1.779E +02 5.408E +02 53.000E +02 1.372E − 03 4.290E − 04 2.705E − 01 8.987E +02 63.600E +02 1.248E − 04 3.903E − 05 1.740E +02 1.252E +03 74.200E +02 1.649E − 04 5.157E − 05 6.782E +00 1.265E +03 84.800E +02 8.522E − 05 2.665E − 05 1.764E +02 1.614E +03 95.400E +02 1.090E − 05 3.409E − 06 1.197E +02 1.737E +03 10 6.000E +02 7.085E − 05 2.215E − 05 −1.798E +02 1.617E +03 Total harmonic distortion = 1.860710E +00 percent Table 2: Analysis printout of the modified circuit, full power (250 W). Fourier components of transient response DC component = 3.755277E − 04 Harm no. Freq (Hz) Fourier comp Normalized comp Phase (Deg) Norm. phase (Deg) 16.000E +01 3.424E +00 1.000E +00 1.800E +02 0.000E +00 21.200E +02 1.028E − 03 3.002E − 04 1.585E +02 −2.015E +02 31.800E +02 4.195E − 03 1.225E − 03 1.890E +01 −5.210E +02 42.400E +02 3.668E − 04 1.071E − 04 1.752E +02 −5.447E +02 53.000E +02 4.809E − 03 1.405E − 03 −1.639E +02 −1.064E +03 63.600E +02 2.352E − 04 6.870E − 05 1.797E +02 −9.001E +02 74.200E +02 1.009E − 03 2.947E − 04 −1.640E +02 −1.424E +03 84.800E +02 1.685E − 04 4.922E − 05 −1.782E +02 −1.618E +03 95.400E +02 3.725E − 04 1.088E − 04 −1.705E +02 −1.790E +03 10 6.000E +02 1.309E − 04 3.824E − 05 −1.777E +02 −1.977E +03 Total harmonic distortion = 1.919198E − 01 percent Thus, the required phase shift of the LPF at the second 9. Simulation Results harmonic frequency is To study the performance of the APFC circuit of Figure 1, the system’s model was simulated by PSPICE circuit simulator. φ = φ − . (37) f 2 v2 The simulation was focused on the performance of the feedback and feed-forward loops under the assumption The error amplifier transfer function is determined primarily that the inner loop is ideal. The inner loop and power by the stability and performance considerations of the stage models were characterized by (4), (5), and (16) outer loop. Consequently, to make the solutions of (34), and implemented in PSPICE according to these behavioral (37) unique, the design of the feed-forward filter should relationships, see Figure 2. The design of the feed-forward be carried out after the complete knowledge of the error LPF and voltage feedback amplifier followed the procedure amplifier characteristics is gained. Note that φ ,asdefined discussedin[15, 16]. The program simulated a closed-loop v2 by (22), is the overall error amplifier phase shift. Since the PFC system fed by a rectified 110 V/60 Hz line and delivers phase shift of a single-pole error amplifier lags from the P = 250 W at V = 400 V to a resistive load of 640 Ω.The av DC initial +180 degrees, due to the inverting configuration, to holdup capacitor of 450 uF was chosen. The overall squarer- about +90, applying (37) requires about 0/360 degrees of LPF multiplier-divider constant, defined by external resistors, was −3 phase shift. Designing the feed-forward path filter according set to k k /k = R /R = 3.9k/910k = 4.286 · 10 . m d s m AC to the amplitude and phase conditions stated above will Current sense resistor used was R = 0.25 Ω. According to ensure minimum distortion of the PFC input current. It Figure 3(b), the feed-forward filter transfer function was: −3 should be emphasized that, under the assumptions made, H = (R /(R + R + R )) = 19.59 · 10 . For these f 0 ff 3 ff 1 ff 2 ff 3 this approach will render a perfect current programming conditions, the numerical value of expression (31)equals signal independent of the APFC power level. K = 110.2[W/V]. 8 Advances in Power Electronics Table 3: Analysis printout of the modified circuit, half power (125 W). Fourier components of transient response DC component = 3.755277E − 04 Harm no. Freq (Hz) Fourier comp Normalized comp Phase (Deg) Norm. phase (Deg) 16.000E +01 1.801E +00 1.000E +00 1.799E +02 0.000E +00 21.200E +02 5.410E −03.004E − 04 1.584E +02 −2.015E +02 31.800E +02 1.431E − 03 7.949E − 04 −2.125E +01 −5.611E +02 42.400E +02 1.938E − 04 1.076E − 04 1.753E +02 −5.444E +02 53.000E +02 2.529E − 03 1.405E − 03 −1.637E +02 −1.063E +03 63.600E +02 1.239E − 04 6.883E − 05 1.798E +02 −8.998E +02 74.200E +02 5.320E − 04 2.955E − 04 −1.638E +02 −1.423E +03 84.800E +02 8.877E − 05 4.930E − 05 −1.781E +02 −1.618E +03 95.400E +02 1.962E − 04 1.090E − 04 −1.704E +02 −1.790E +03 10 6.000E +02 6.895E − 05 3.829E − 05 −1.776E +02 −1.977E +03 Total harmonic distortion = 1.677760E − 01 percent e H ωC ωC H + 54 db H + 54 db −50 H e e −50 SEL≫ SEL≫ DB(V(e)) DB(V ( fm)) + 54 DB(V(e)/V(out)) DB(V(e)) DB(V ( fm))+54 DB(V(e)/V(out)) 120 Hz 120 Hz ∠H ∠H ∠H − 90 f e ∠H − 90 0 0 0.1 Hz 1 Hz 10 Hz 100 Hz 1 kHz 10 kHz 0.1 Hz 1 Hz 10 Hz 100 Hz 1 kHz 10 kHz Frequency, f Frequency, f P(V(e)) P(V(e)) P(V ( fm)) + 360 P(V ( fm)) + 360 (a) (b) Figure 5: Frequency response of the error amplifier, H , and the feed-forward network, H , in the original design (a) and the modified e f design (b). Notice that the magnitude and phase conditions are satisfied at the vicinity of the second-line harmonic frequency. To demonstrate the validity of the proposed ripple reduced to a negligible level of only 0.19%, see Table 2. That cancellation method, the LPF of the feed-forward network is about one order of magnitude improvement of THD. was modified to follow (34)and (37) as shown at Figure 3(b). New values were given to the error amplifier parameters as depicted in Figure 3(c). The simulation results of the 10. Conclusions original and proposed circuits are presented in Figures 4(a) and 4(b). Here, the normalized outputs of the voltage One of the main sources of input current distortion in error amplifier, feed-forward, and divider circuits are shown. high-frequency APFC systems is the output voltage ripple Comparison of the results reveals that the amplitude of the which propagates into the feedback loop as well as the ripple voltage at the divider output is greatly reduced by the second harmonic of the line voltage injected through the proposed method, reducing also the THD of the simulated feed-forward loop. These signals adversely affect the current APFC system. The normalized rectified line voltage and reference signal quality. current as well as the APFC’s charging currents are shown This paper examined the propagation of the ripple com- in Figure 4(c). Fourier analysis was carried out by SPICE on ponents in the feedback and feed-forward loops of the APFC the simulated line current. Fourier analysis results are given controller circuits and their interaction within the current in Tables 1, 2 and 3. The analysis reveals that the distorted shaping network. Based on this analysis, a ripple cancella- current programming signal of the original design, see tion method is proposed. Analytical results are confirmed Table 1, contributes 1.86% to the total harmonic distortion by simulation and show good agreement with predicted of the APFC system, which is rather good performance theoretical results. The simulation results suggest that the index, whereas, using the proposed method the distortion is proposed method can reduce the THD of the input current Mag (db) Phase (Deg) Mag (db) Phase (deg) Advances in Power Electronics 9 of PFC system by more than an order of magnitude. The [11] J. P. Gegner and C. Q. Lee, “Linear peak current mode control: a simple active power factor correction control technique for present analysis and simulation were carried out under some continuous conduction mode,” in Proceedings of the 27th Ann- simplifying assumptions, yet, second-order effects proved to ual IEEE Power Electronics Specialists Conference (PESC ’96), be negligible. pp. 196–202, January 1996. Another important advantage of the proposed method [12] Z. Lai and K. M. Smedley, “Family of power-factor-correction is a dramatic increase of the error amplifier bandwidth, see controllers,” in Proceedings of the IEEE 12th Applied Power Figure 5. This is possible in view of the fact that effective Electronics Conference (APEC ’97), pp. 66–73, February 1997. ripple cancellation requires a lesser amount of error amplifier [13] J. Rajagopalan, F. C. Lee, and P. Nora, “Generalized technique attenuation of the second-line harmonic. Therefore, the forderivationofaverage currentmodecontrol laws forpower outer feedback loop bandwidth becomes dominated by the factor correction without input voltage sensing,” in Proceed- relatively large holding capacitor, which value is determined ings of the IEEE 12th Applied Power Electronics Conference,pp. primarily by the energy storage requirements. 81–87, February 1997. The discussion of this paper is confined to the topology of [14] S. Ben-Yaakov and I. Zeltser, “The dynamics of a PWM boost one family of APFC controllers (Figure 1); however, the pro- converter with resistive input,” IEEE Transactions on Industrial posed approach could be expanded to other APFC schemes Electronics, vol. 46, no. 3, pp. 613–619, 1999. by following the idea of ripple compensation developed here. [15] P. C. Todd, “UC3854 controlled power factor correction circuit design,” U-134 Application note, Unitrode Integrated Circuits. References [16] J. B. Williams, “Design of feedback loop in unity power factor AC to DC converter,” in Proceedings of the 20th Annual IEEE [1] K. N. Sakthivel, S. K. Das, and K. R. Kini, “Importance of Power Electronics Specialists Conference (PESC ’89), pp. 959– quality AC power distribution and understanding of EMC 967, June 1989. standards IEC, 61000-3-2, IEC, 61000-3-3 & IEC, 61000- [17] L. H. Dixon, “High power factor preregulators for offline 3-11,” in Proceedings of the 8th International Conference on power supplies,” in Proceedings of the Unitrode Seminar, 1993. Electromagnetic Interference and Compatibility, pp. 423–430, [18] L. H. Dixon, “High power factor preregulator design optimiza- tion,” in Proceedings of the Unitrode Seminar, 1992. [2] B. Singh, B. N. Singh, A. Chandra, K. Al-Haddad, A. Pandey, and D. P. Kothari, “A review of single-phase improved power quality AC-DC converters,” IEEE Transactions on Industrial Electronics, vol. 50, no. 5, pp. 962–981, 2003. [3] M. M. Jovanovic´ and Y. Jang, “State-of-the-art, single-phase, active power-factor-correction techniques for high-power applications—an overview,” IEEE Transactions on Industrial Electronics, vol. 52, no. 3, pp. 701–708, 2005. [4] B. Andreycak, “Power factor correction using UC3852 con- trolled on-time zero current switching technique,” U-132 Application note, Unitrode Integrated Circuits. [5] M. Marvi and A. Fotowat-Ahmady, “A fully ZVS critical conduction mode boost PFC,” IEEE Transactions on Power Electronics, vol. 27, no. 4, pp. 1958–1965, 2012. [6] T. F. Wu, J. R. Tsai, Y. M. Chen, and Z. H. Tsai, “Integrated circuits of a PFC controller for interleaved critical-mode boost converters,” in Proceedings of the 22nd Annual IEEE Applied Power Electronics Conference and Exposition (APEC ’07),pp. 1347–1350, March 2007. [7] J.R.Tsai, T. F. Wu,C.Y.Wu, Y. M. Chen,and M. C. Lee, “Interleaving phase shifters for critical-mode boost PFC,” IEEE Transactions on Power Electronics, vol. 23, no. 3, pp. 1348– 1357, 2008. [8] K. De Gusseme, ´ D. M. Van de Sype, A. P. M. Van den Bossche, and J. A. Melkebeek, “Input-current distortion of CCM boost PFC converters operated in DCM,” IEEE Transactions on Industrial Electronics, vol. 54, no. 2, pp. 858–865, 2007. [9] K. H. Liu and Y. L. Lin, “Current waveform distortion in power factor correction circuits employing discontinuous- mode boost converters,” in Proceedings of the 20th Annual IEEE Power Electronics Specialists Conference (PESC ’89), pp. 825– 829, June 1989. [10] D. Maksimovic, ´ Y. Jang, and R. W. Erickson, “Nonlinear- carrier control for high-power-factor boost rectifiers,” IEEE Transactions on Power Electronics, vol. 11, no. 4, pp. 578–584, 1996. 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Controller Design Considerations for ACM APFC Systems

Abramovitz, Alexander
Advances in Power Electronics , Volume 2012 – Oct 30, 2012
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Hindawi Publishing Corporation
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Copyright © 2012 Alexander Abramovitz. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.
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2090-181X
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10.1155/2012/286861
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Hindawi Publishing Corporation Advances in Power Electronics Volume 2012, Article ID 286861, 9 pages doi:10.1155/2012/286861 Research Article Alexander Abramovitz Department of Electrical Engineering and Computer Science, University of California, Irvine, CA 92697, USA Correspondence should be addressed to Alexander Abramovitz, alabr@hotmail.com Received 27 February 2012; Revised 6 August 2012; Accepted 7 August 2012 Academic Editor: C. M. Liaw Copyright © 2012 Alexander Abramovitz. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited. This paper is concerned with performance of the current shaping network in Average Current Mode (ACM) Active Power Factor Correction (APFC) systems. Theoretical expressions for the ripple components are derived. Then, ripple interaction and impact on the current loop reference signal are investigated. A modification of the controller network is suggested that results in an improved Total Harmonic Distortion (THD). Design guidelines are suggested. The theoretical predictions were validated by simulation. 1. Introduction of the implementation, however, the duty cycle program- ming is implemented according to the converters input port Over the past few years, a variety of current shaping method- ideal average relationships and ideal modulator ramp signal. ologiesweredeveloped forActivePower Factor Correction As a result, accurate current loop operation can only be (APFC) [1–3]. Each approach undertaken is a compromise in attained in the Continuous Conduction Mode (CCM) under between the performance indexes and the circuit complexity negligible current ripple conditions. In practice, however, andcost. TheCriticalConductionMode(CrCM)APFC the CCM-DCM mode changes, current ripple, and ramp operating on the CCM-DCM boundary [4–7] shapes the carrier imperfections cause the duty cycle to deviate from the average input current by comparator/zero detector and ideal relationship resulting in distortion in the average input is unconditionally stable. However, the natural simplicity, current. robustness, and stability of CrCM APFC are offset by The very proper average current mode three-loop APFC high ripple current which cause increased conduction and [15–18] achieves its control objectives by a control scheme core losses. Difficulties in filtering the variable frequency shown at Figure 1. The three-loop APFC uses a slow outer current ripple and poor efficiency restrict this technique to voltage loop to control the output voltage and a fast current low-power and low-cost applications. Other Discontinuous loop for active shaping of the average input current. The Conduction Mode (DCM) based designs, which upside is reference signal for the inner current loop is derived from the simplicity suffer from similar problems exhibiting also higher rectified power line voltage by the multiplier-squarer-divider harmonic distortion of the line current [8, 9]. circuit. Additional outer feed-forward loop compensates for APFC without line voltage sensing, [10–13] stands out as the line voltage variations. Such an APFC could be designed a robust, technologically simple, and cost-effective solution. to operate in CCM most of the cycle but could tolerate also A simple and clear physical insight into the principle of DCM intervals sustaining good current tracking. operation of the current loop of this class of APFCs was The two feedback loops of the APFC of Figure 1 have suggested in [14]. All of the mentioned above APFCs with conflicting objectives. In particular, a strong outer loop that no input voltage sensing make use of a hidden current loop manages to stabilize the output voltage will deteriorate the inside a DC-DC converter. The designs mainly differ in their power factor by dictating an input current that ensures method of realization of the transresistive feedback, PWM, a fixed output voltage rather than the desired sinusoidal- and supplementary current loop control circuitry. Regardless shaped current. The outer loop is usually designed with 2 Advances in Power Electronics L V D I o ch AC v (θ) out i (θ) v in AC CA PWM cp v v d e − DIV VA MULT + V ref ff SQR LPF Figure 1: Three-loop ACM APFC system block diagram. a limited bandwidth as well as with a low gain so to distortion components, which originate in the outer loops. heavily attenuate the output ripple. Otherwise, the ripple will Based on the results, the requirements for maintaining distort the input current by penetrating into the reference a distortion-free current reference are formulated. Finally, of the current loop. As a result the response of the outer under the assumption of the ideal current loop, the residual loop to load variations is rather slow. The outer loop error distortion caused by the proposed ripple cancellation scheme amplifier output voltage contains a second harmonic ripple is examined. component which modulates the current amplitude and thus distorts the current reference signal. Obviously, this also 3. General Considerations: Review of results in distorted line current. APFC Output Current and Voltage This paper suggests that one of the causes of the major current distortion in most, if not all, APFC systems is the sec- Under the assumptions above, the line voltage and current of ond harmonic ripple components that are brought into the the APFC of Figure 1 are in phase and of a sinusoidal shape. current reference by the outer loops. The proposed solution To simplify the notation the analyses are confined to one- to the problem can be found by compensating the output half of the line period for which the rectified inputs can be ripple rather than filtering. This alternative was investigated expressed as in this study analytically and by simulation. It was found that such a strategy is possible and furthermore it can easily be v (θ) = V sin θ, in m implemented by simple additional circuitry to commercially (1) i (θ) = I sin θ, in m available APFC controllers. This paper presents the theory of the proposed approach and demonstrates the improvement where θ = ωt is the power line angle (0 ≤ θ ≤ π). The ins- in Total Harmonic Distortion (THD) that can be gained and tantaneous input power of the APFC is given by provides design guidelines. p (θ) = v (θ)i (θ) = V I sin θ = P (1 − cos 2θ), in in in m m av (2) 2. Basic Assumptions and Strategy where P = (1/2)V I is the average power over the power av m m The analyses to follow are carried under the following assum- line cycle. The instantaneous charging power at the output of ptions: the APFC is a function of the output voltage, v (θ), and the out (a) the line voltage is a pure sinusoidal wave; output charging current, i (θ): ch (b) the rectifiers are ideal; p (θ) = v (θ)i (θ) ≈ V i (θ). out out ch DC ch (3) (c) the power stage is linear and 100% efficient; Here, the output ripple is neglected, that is, the output (d) the current loop is ideal, that is, it forces the input voltage, v (θ), of the APFC is assumed to be equal to its out current to follow the reference signal; average value, V . For an ideal power stage with 100% DC (e) the holdup capacitor is large and hence the output efficiency, instantaneous input and output power are equal: ripple is small as compared to the dc output voltage. p (θ) = p (θ). (4) in out The following approach is adopted: initially it is assumed Applying (2)–(4), the charging current, i (θ), is approxi- ch that the input current is a pure sine wave. Next, the outer mated to loop ripple components propagation mechanism into the current reference circuit is investigated. The assumption of av i (θ) = (1 − cos 2θ). (5) ch the ideal current loop helps identify the current reference DC Load Advances in Power Electronics 3 Figure 2: Simulation diagram of the modified three-loop APFC based on the behavioral model. The holding capacitor current, i (θ), is the difference bet- where V = (2/π)V , V = −(4/3π)V , V = c i0 m i2 m i4 ween the charging current and the DC load currents: −(4/15π)V , and so forth are the Fourier coefficients. The relative phases of the harmonics are zero. When this av i (θ) = i (θ) − I = − cos 2θ. (6) signal is fed to the LPF feed-forward network of Figure 2, c ch DC DC the LPF output voltage, v (θ), appears as The AC current of the holdup capacitor, i (θ), generates a second harmonics ripple component, v (θ), which appears o2 v (θ) = V H + V H cos 2θ + φ f i0 f 0 i2 f 2 f 2 at the output: (12) + V H cos 4θ + φ +··· , 1 −P i4 f 4 f 4 av v (θ) = i (θ)dθ = sin 2θ. o2 c (7) ωC 2ωCV DC where H and φ are the gain and phase of the LPF transfer f n f n Clearly, the output ripple is a linear function of power. The function at the nth harmonic of the line frequency. Since the instantaneous output voltage including the second harmonic amplitude of the harmonics of the rectified voltage decreases ripple can now be written as with their frequency and since the LPF provides sufficient attenuation at high frequencies, harmonic components v (θ) = V + v (θ). (8) out DC o2 higher than the second one may be neglected at the output of Using (7) yields the LPF. Therefore, the response of the LPF is approximated to av v (θ) = V 1 − sin 2θ . (9) out DC 2ωCV DC V i2 f 2 v (θ) = V H 1+ cos 2θ + φ . (13) f i0 f 0 f 2 V H The second harmonic frequency peak-to-peak ripple, γ,is i0 f 0 derived from the above to be The v (θ) signal is squared with the gain of k by the squarer f s ΔV out P pp av γ = 100% = 100%. (10) circuit, see Figure 1. Applying the same reasoning as above V ωCV DC DC the resulting quadratic term could be neglected. Therefore, the approximated feed-forward signal is 4. The Feed-Forward Path Signal ( ) v θ ff The rectified input voltage fed to the feed-forward path filter (LPF) of the PFC topology under study, see Figure 1,can be V f 2 i2 2 2 2 = k v (θ) ≈ k V H 1+2 cos 2θ + φ . represented by the Fourier series: s s f 2 f i0 f 0 V H i0 f 0 v (θ) = V + V cos 2θ + V cos 4θ +··· , (11) in i0 i2 i4 (14) 4 Advances in Power Electronics Substituting the values of the Fourier coefficients, the expres- The second harmonic component, v (θ), appears as the res- e2 sion for the feed-forward signal fed to the divider is obtained ponse of the error amplifier to the output voltage ripple, as v (θ), given by (7) o2 H P v2 av v (θ) = V v (θ), (15) ff ff 0 ff n v (θ) = − sin 2θ + φ . (22) e2 v2 2ωC V DC 2 2 2 where the term, V = k (4/π )V H and v (θ) is the ff 0 s ff n m f 0 Here, the error amplifier’s gain and phase, at the frequency of normalized feed-forward voltage: the second harmonic, are denoted H and φ respectively. v2 v2 Combining (20), (21), and (22), yields the expression for the v (θ) H ff 4 f 2 error amplifier output voltage delivered to the input of the v (θ) = = 1 − cos 2θ + φ . ff n f 2 (16) V 3 H ff 0 f 0 divider as Equation (15) describes a waveform having a DC value v (θ) = V v (θ), (23) e e0 en proportional to the square of the amplitude of the input where v (θ) is the normalized feedback voltage: en voltage, V , scaled by the DC gain of the feed-forward 2 2 v K H path: k (4/π )H . The normalized feed-forward signal e(θ) v2 f 0 v (θ) = = 1 − sin 2θ + φ . (24) en v2 V 4V ωC (16) contains an undesirable second harmonic component e0 DC propagating into the current reference. Interesting to note Note that the normalized second harmonic ripple compo- is that the normalized ripple (16) at the output of the nent at the output of the error amplifier is constant and inde- LPF is constant and depends on the attenuation at the pendent of the power level output voltage of the APFC. This second harmonic frequency, (4/3)(H /H ). The amount f 2 f 0 observation forms the basis for the following development of of attenuation is determined by LPF configuration and its the proposed ripple cancellation method. comer frequency. Lowering the corner frequency increases the attenuation, lowering also the harmonic contents of the 6. The Current Programming Signal feed-forward signal. This results in better line current quality. However, lowering the corner frequency slows the APFC To produce the correct current programming signal, the response to line variations. APFC circuit of Figure 1 uses the divider output, v (θ), to modulate the line voltage waveform. The divider output sig- 5. The Voltage Feedback Path Signal nal is calculated using (15)and (23) yielding ⎛ ⎞ To establish the operating point of the voltage error amplifier v (θ) π k P e d av ⎝ ⎠ v (θ) = k = v (θ). (25) d d dn the issue of the input current generation should be addressed v (θ) 2 k KH V ff s f 0 first. The input current of the PFC circuit of Figure 1 is gen- Here, k is the divider gain constant and v (θ) is the nor- erated by the following algorithm: d dn malized divider output: 1 − (K/4V )(H /ωC) sin 2θ + φ i (θ) = I sin θ = K(v (θ)) (V sin θ). (17) v (θ) in m e m en DC v2 v2 V v (θ) = = . dn v (θ) ff n 1 − (4/3) H /H cos 2θ + φ f 2 f 0 f 2 where, v (θ) is the voltage feedback error amplifier signal and (26) K is the system’s gain constant. Thus the amplitude of the The current programming signal, v (θ), produced by mod- cp input current and the average input power are ulation of the line voltage (1) with the divider output (25)is v (θ) given by I = K , (18) v (θ) = k v (θ)v (θ) cp m d in I V K ⎛ ⎞ m m P = = v (θ). (19) av e (27) π k k 1 P 2 2 m d av ⎝ ⎠ = v (θ) sin(θ), dn 2 k KH V s m f 0 The advantage of the feed-forward path is apparent; the APFC power level (19) is independent of the line voltage. where k is the multiplier gain constant. The current pro- The steady-state output voltage of the error amplifier, gramming signal amplitude is therefore v (θ), contains the DC term, V , as well as the second har- e e0 ⎛ ⎞ monics ripple component, v (θ): π k k 1 P e2 m d av ⎝ ⎠ v = v (θ). (28) cpm dn 2 k KH V s m f 0 v (θ) = V + v (θ). (20) e e0 e2 Equations (27)and (28) reveal the mechanism by which The steady state DC error amplifier voltage, V ,requiredto e0 distortion components of the outer loops are introduced into maintain the average power level, P , could be derived from av the current reference. The term v (θ) contains harmonic dn (19) neglecting the ripple component as components which modulates the current programming signal amplitude (28). Consequently, the input current of the (21) V = P . e0 av APFC could not possibly be any less distorted than (27). K Advances in Power Electronics 5 v (θ) in v (θ) in R R si sf R ff2 ff1 R 100 k 100 k ff1 ff2 v (θ) 910 k 91 k f 910 k 91 k v (θ) R 150 k C C ff3 ff1 ff2 C C ff2 ff1 R C ff3 s 20 k 0.1 μF 0.47 μF 0.1 μF 0.2 μF 20 k 0.1 μF (a) (b) out C 80 nF vf (6.5 nF) vi R 177 k vf 510 k (200 k) (910 k) vd ref 9.76 k 7.5 V (17.4 k) (c) Figure 3: APFC feed-forward filters: original design (a); modified (b); voltage error amplifier configuration with original and modified (in brackets) values (c). 7. The Power Gain Constant for the following reasons. To ensure stability and adequate phase margin, the error amplifier usually has a single-pole When the current loop tightly regulates the input current, the transfer function of −20 db/decade gain roll off beyond its output voltage of the current sensing network, v (θ), see sense corner frequency and its filtering action is poor. Since the Figure 1, is forced to follow the current programming signal, ripple frequency is quite low the bandwidth of the error v (θ): cp amplifier is severely restricted resulting in poor transient response. A high-order low-pass filter may be used to achieve v (θ) = v (θ). sense cp (29) efficient filtering of the average component of the rectified input voltage. However, once again due to the low second In the most common case, the current sensing network is just harmonic frequency the filter has a narrow bandwidth and a series resistance, R , so the amplitude of the sensed voltage its transient response is rather poor. Here an alternative is approach is proposed. Equations (27)and (28) suggest that av it is possible to achieve distortion-free current programming V = I R = 2 R . (30) sense m s s V signal by making the normalized divider output (26)equal unity: The power gain constant K may be found substituting (28), (30) into (29) and assuming an ideal v (θ), that is, (26) dn 1 − (K/4V )(H /ωC) sin 2θ + φ DC v2 v2 equals unity. This gives v (θ) = = 1. dn (32) 1 − (4/3) H /H cos 2θ + φ f 2 f 0 f 2 π k k 1 m d K = . (31) 4 k R H s s f 0 To satisfy (32) requires that the normalized ripple compo- nents of the error and the feed-forward signals be equal both This relationship remains valid also for the general case, in amplitude and phase: when the current sensing network transfer function low fre- quency gain is denoted by R . K H 4 f 2 v2 sin 2θ + φ = cos 2θ + φ . (33) v2 f 2 4V ωC 3 H DC f 0 8. Filter Design for Minimum Line Current Distortion Since the normalized ripple components are of the same frequency and of a constant amplitude, it is possible to fulfill Examination of (27)and (28) reveals that any harmonic (34) by proper controller circuit design. For this purpose disturbances at the divider output will produce cross prod- both amplitude and phase conditions must be satisfied. The ucts with the sine term. This will appear as harmonics in amplitude condition defines the LPF attenuation needed to the current programming signal and cause distortion in the equate the amplitudes of the ripple components: input current. Traditionally, the designers [15–18] minimize the distortion by providing large attenuation of the second 3K H harmonic, that is, minimizing the H and H terms in f 2 v2 v2 f 2 = . (34) (16), (24), and (26). However, this has only a limited success H 8V (2ω)C f 0 DC 6 Advances in Power Electronics 1.04 1.08 dn 1.02 1.04 dn en ffn 0.98 0.96 en ffn 0.96 0.92 335 336 338 340 342 344 346 348 325.9 328 332 336 340 344 347 Time (ms) Time (ms) V(div)/1.18 V(sqr)/3.7345 V(e)/4.412 V(e)/4.824 V(sqr)/3.7424 V(div)/1.29 (a) (b) 1.08 1.04 dn ffn 0.96 en 0.92 326 328 332 336 340 344 347 Time (ms) V(sqr)/3.735 V(e)/2.5356 V(div)/0.678 (c) i norm line norm line norm i norm 0.5 ch norm SEL≫ −2 0 200 202 204 206 208 210 212 214 216 200 202 204 206 208 210 212 214 216 Time (ms) Time (ms) V(rec)/155 V(out)/400 V(line)/155 I (V )/6.6382 rs I (G )/2.562 −I(Vline)/6.6382 2 (d) Figure 4: Normalized voltages of the error amplifier v , the feed-forward network v , and the divider output v , in the original design en ff n dn (250 W) (a); modified design (250 W) (b), Modified design (125 W) (c), Modified design waveforms of the normalized rectified voltage V , in converter’s input current I , and the APFC’s charging current I (d). in ch This could be rearranged using (31) into the following form: The phase condition could be derived by equating the sine and cosine terms in (33) and using elementary trigo- nometry relationship: 3π k k m d H = H , f 2 v2 (35) 128fCR H V k s f 0 DC s cos 2θ + φ = sin 2θ + φ = cos 2θ + φ − . (36) f 2 v2 v2 where, f is the line frequency. (V) (V) (V) Advances in Power Electronics 7 Table 1: Analysis printout of the original circuit, full power (250 W). Fourier components of transient response DC component = 2.758333E − 04 Harm no. Freq (Hz) Fourier comp Normalized comp Phase (Deg) Norm. phase (Deg) 16.000E +01 3.198E +00 1.000E +00 −1.797E +02 0.000E +00 21.200E +02 4.295E − 04 1.343E − 04 1.456E +02 5.050E +02 31.800E +02 5.949E − 02 1.860E − 02 1.742E +01 5.565E +02 42.400E +02 1.831E − 04 5.724E − 05 −1.779E +02 5.408E +02 53.000E +02 1.372E − 03 4.290E − 04 2.705E − 01 8.987E +02 63.600E +02 1.248E − 04 3.903E − 05 1.740E +02 1.252E +03 74.200E +02 1.649E − 04 5.157E − 05 6.782E +00 1.265E +03 84.800E +02 8.522E − 05 2.665E − 05 1.764E +02 1.614E +03 95.400E +02 1.090E − 05 3.409E − 06 1.197E +02 1.737E +03 10 6.000E +02 7.085E − 05 2.215E − 05 −1.798E +02 1.617E +03 Total harmonic distortion = 1.860710E +00 percent Table 2: Analysis printout of the modified circuit, full power (250 W). Fourier components of transient response DC component = 3.755277E − 04 Harm no. Freq (Hz) Fourier comp Normalized comp Phase (Deg) Norm. phase (Deg) 16.000E +01 3.424E +00 1.000E +00 1.800E +02 0.000E +00 21.200E +02 1.028E − 03 3.002E − 04 1.585E +02 −2.015E +02 31.800E +02 4.195E − 03 1.225E − 03 1.890E +01 −5.210E +02 42.400E +02 3.668E − 04 1.071E − 04 1.752E +02 −5.447E +02 53.000E +02 4.809E − 03 1.405E − 03 −1.639E +02 −1.064E +03 63.600E +02 2.352E − 04 6.870E − 05 1.797E +02 −9.001E +02 74.200E +02 1.009E − 03 2.947E − 04 −1.640E +02 −1.424E +03 84.800E +02 1.685E − 04 4.922E − 05 −1.782E +02 −1.618E +03 95.400E +02 3.725E − 04 1.088E − 04 −1.705E +02 −1.790E +03 10 6.000E +02 1.309E − 04 3.824E − 05 −1.777E +02 −1.977E +03 Total harmonic distortion = 1.919198E − 01 percent Thus, the required phase shift of the LPF at the second 9. Simulation Results harmonic frequency is To study the performance of the APFC circuit of Figure 1, the system’s model was simulated by PSPICE circuit simulator. φ = φ − . (37) f 2 v2 The simulation was focused on the performance of the feedback and feed-forward loops under the assumption The error amplifier transfer function is determined primarily that the inner loop is ideal. The inner loop and power by the stability and performance considerations of the stage models were characterized by (4), (5), and (16) outer loop. Consequently, to make the solutions of (34), and implemented in PSPICE according to these behavioral (37) unique, the design of the feed-forward filter should relationships, see Figure 2. The design of the feed-forward be carried out after the complete knowledge of the error LPF and voltage feedback amplifier followed the procedure amplifier characteristics is gained. Note that φ ,asdefined discussedin[15, 16]. The program simulated a closed-loop v2 by (22), is the overall error amplifier phase shift. Since the PFC system fed by a rectified 110 V/60 Hz line and delivers phase shift of a single-pole error amplifier lags from the P = 250 W at V = 400 V to a resistive load of 640 Ω.The av DC initial +180 degrees, due to the inverting configuration, to holdup capacitor of 450 uF was chosen. The overall squarer- about +90, applying (37) requires about 0/360 degrees of LPF multiplier-divider constant, defined by external resistors, was −3 phase shift. Designing the feed-forward path filter according set to k k /k = R /R = 3.9k/910k = 4.286 · 10 . m d s m AC to the amplitude and phase conditions stated above will Current sense resistor used was R = 0.25 Ω. According to ensure minimum distortion of the PFC input current. It Figure 3(b), the feed-forward filter transfer function was: −3 should be emphasized that, under the assumptions made, H = (R /(R + R + R )) = 19.59 · 10 . For these f 0 ff 3 ff 1 ff 2 ff 3 this approach will render a perfect current programming conditions, the numerical value of expression (31)equals signal independent of the APFC power level. K = 110.2[W/V]. 8 Advances in Power Electronics Table 3: Analysis printout of the modified circuit, half power (125 W). Fourier components of transient response DC component = 3.755277E − 04 Harm no. Freq (Hz) Fourier comp Normalized comp Phase (Deg) Norm. phase (Deg) 16.000E +01 1.801E +00 1.000E +00 1.799E +02 0.000E +00 21.200E +02 5.410E −03.004E − 04 1.584E +02 −2.015E +02 31.800E +02 1.431E − 03 7.949E − 04 −2.125E +01 −5.611E +02 42.400E +02 1.938E − 04 1.076E − 04 1.753E +02 −5.444E +02 53.000E +02 2.529E − 03 1.405E − 03 −1.637E +02 −1.063E +03 63.600E +02 1.239E − 04 6.883E − 05 1.798E +02 −8.998E +02 74.200E +02 5.320E − 04 2.955E − 04 −1.638E +02 −1.423E +03 84.800E +02 8.877E − 05 4.930E − 05 −1.781E +02 −1.618E +03 95.400E +02 1.962E − 04 1.090E − 04 −1.704E +02 −1.790E +03 10 6.000E +02 6.895E − 05 3.829E − 05 −1.776E +02 −1.977E +03 Total harmonic distortion = 1.677760E − 01 percent e H ωC ωC H + 54 db H + 54 db −50 H e e −50 SEL≫ SEL≫ DB(V(e)) DB(V ( fm)) + 54 DB(V(e)/V(out)) DB(V(e)) DB(V ( fm))+54 DB(V(e)/V(out)) 120 Hz 120 Hz ∠H ∠H ∠H − 90 f e ∠H − 90 0 0 0.1 Hz 1 Hz 10 Hz 100 Hz 1 kHz 10 kHz 0.1 Hz 1 Hz 10 Hz 100 Hz 1 kHz 10 kHz Frequency, f Frequency, f P(V(e)) P(V(e)) P(V ( fm)) + 360 P(V ( fm)) + 360 (a) (b) Figure 5: Frequency response of the error amplifier, H , and the feed-forward network, H , in the original design (a) and the modified e f design (b). Notice that the magnitude and phase conditions are satisfied at the vicinity of the second-line harmonic frequency. To demonstrate the validity of the proposed ripple reduced to a negligible level of only 0.19%, see Table 2. That cancellation method, the LPF of the feed-forward network is about one order of magnitude improvement of THD. was modified to follow (34)and (37) as shown at Figure 3(b). New values were given to the error amplifier parameters as depicted in Figure 3(c). The simulation results of the 10. Conclusions original and proposed circuits are presented in Figures 4(a) and 4(b). Here, the normalized outputs of the voltage One of the main sources of input current distortion in error amplifier, feed-forward, and divider circuits are shown. high-frequency APFC systems is the output voltage ripple Comparison of the results reveals that the amplitude of the which propagates into the feedback loop as well as the ripple voltage at the divider output is greatly reduced by the second harmonic of the line voltage injected through the proposed method, reducing also the THD of the simulated feed-forward loop. These signals adversely affect the current APFC system. The normalized rectified line voltage and reference signal quality. current as well as the APFC’s charging currents are shown This paper examined the propagation of the ripple com- in Figure 4(c). Fourier analysis was carried out by SPICE on ponents in the feedback and feed-forward loops of the APFC the simulated line current. Fourier analysis results are given controller circuits and their interaction within the current in Tables 1, 2 and 3. The analysis reveals that the distorted shaping network. Based on this analysis, a ripple cancella- current programming signal of the original design, see tion method is proposed. Analytical results are confirmed Table 1, contributes 1.86% to the total harmonic distortion by simulation and show good agreement with predicted of the APFC system, which is rather good performance theoretical results. The simulation results suggest that the index, whereas, using the proposed method the distortion is proposed method can reduce the THD of the input current Mag (db) Phase (Deg) Mag (db) Phase (deg) Advances in Power Electronics 9 of PFC system by more than an order of magnitude. The [11] J. P. Gegner and C. Q. Lee, “Linear peak current mode control: a simple active power factor correction control technique for present analysis and simulation were carried out under some continuous conduction mode,” in Proceedings of the 27th Ann- simplifying assumptions, yet, second-order effects proved to ual IEEE Power Electronics Specialists Conference (PESC ’96), be negligible. pp. 196–202, January 1996. Another important advantage of the proposed method [12] Z. Lai and K. M. Smedley, “Family of power-factor-correction is a dramatic increase of the error amplifier bandwidth, see controllers,” in Proceedings of the IEEE 12th Applied Power Figure 5. This is possible in view of the fact that effective Electronics Conference (APEC ’97), pp. 66–73, February 1997. ripple cancellation requires a lesser amount of error amplifier [13] J. Rajagopalan, F. C. Lee, and P. Nora, “Generalized technique attenuation of the second-line harmonic. Therefore, the forderivationofaverage currentmodecontrol laws forpower outer feedback loop bandwidth becomes dominated by the factor correction without input voltage sensing,” in Proceed- relatively large holding capacitor, which value is determined ings of the IEEE 12th Applied Power Electronics Conference,pp. primarily by the energy storage requirements. 81–87, February 1997. The discussion of this paper is confined to the topology of [14] S. Ben-Yaakov and I. Zeltser, “The dynamics of a PWM boost one family of APFC controllers (Figure 1); however, the pro- converter with resistive input,” IEEE Transactions on Industrial posed approach could be expanded to other APFC schemes Electronics, vol. 46, no. 3, pp. 613–619, 1999. by following the idea of ripple compensation developed here. [15] P. C. Todd, “UC3854 controlled power factor correction circuit design,” U-134 Application note, Unitrode Integrated Circuits. References [16] J. B. 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Jang, “State-of-the-art, single-phase, active power-factor-correction techniques for high-power applications—an overview,” IEEE Transactions on Industrial Electronics, vol. 52, no. 3, pp. 701–708, 2005. [4] B. Andreycak, “Power factor correction using UC3852 con- trolled on-time zero current switching technique,” U-132 Application note, Unitrode Integrated Circuits. [5] M. Marvi and A. Fotowat-Ahmady, “A fully ZVS critical conduction mode boost PFC,” IEEE Transactions on Power Electronics, vol. 27, no. 4, pp. 1958–1965, 2012. [6] T. F. Wu, J. R. Tsai, Y. M. Chen, and Z. H. Tsai, “Integrated circuits of a PFC controller for interleaved critical-mode boost converters,” in Proceedings of the 22nd Annual IEEE Applied Power Electronics Conference and Exposition (APEC ’07),pp. 1347–1350, March 2007. [7] J.R.Tsai, T. F. Wu,C.Y.Wu, Y. M. Chen,and M. C. Lee, “Interleaving phase shifters for critical-mode boost PFC,” IEEE Transactions on Power Electronics, vol. 23, no. 3, pp. 1348– 1357, 2008. [8] K. De Gusseme, ´ D. M. Van de Sype, A. P. M. Van den Bossche, and J. A. Melkebeek, “Input-current distortion of CCM boost PFC converters operated in DCM,” IEEE Transactions on Industrial Electronics, vol. 54, no. 2, pp. 858–865, 2007. [9] K. H. Liu and Y. L. Lin, “Current waveform distortion in power factor correction circuits employing discontinuous- mode boost converters,” in Proceedings of the 20th Annual IEEE Power Electronics Specialists Conference (PESC ’89), pp. 825– 829, June 1989. [10] D. Maksimovic, ´ Y. Jang, and R. W. Erickson, “Nonlinear- carrier control for high-power-factor boost rectifiers,” IEEE Transactions on Power Electronics, vol. 11, no. 4, pp. 578–584, 1996. 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