Get 20M+ Full-Text Papers For Less Than $1.50/day. Start a 14-Day Trial for You or Your Team.

Learn More →

High-Performance Ternary (4:2) Compressor Based on Capacitive Threshold Logic

High-Performance Ternary (4:2) Compressor Based on Capacitive Threshold Logic AbstractThis paper presents a ternary (4:2) compressor, which is an important component in multiplication. However, the structure differs from the binary counterpart since the ternary model does not require carry signals. The method of capacitive threshold logic (CTL) is used to achieve the output signals directly. Unlike the previously presented similar structure, the entire capacitor network is divided into two parts. This segregation results in higher reliability and robustness against unwanted process, voltage, and temperature (PVT) variations. Simulations are performed by HSPICE and 32nm CNFET technology. Simulation results demonstrate about 94% higher performance in terms of power-delay product (PDP) for the new design over the previous one. http://www.deepdyve.com/assets/images/DeepDyve-Logo-lg.png International Journal of Electronics and Telecommunications de Gruyter

High-Performance Ternary (4:2) Compressor Based on Capacitive Threshold Logic

Download PDF
7 pages

Loading next page...
 
/lp/de-gruyter/high-performance-ternary-4-2-compressor-based-on-capacitive-threshold-6GndLuSvDJ
Publisher
de Gruyter
Copyright
© by Reza Faghih Mirzaee
ISSN
2300-1933
eISSN
2300-1933
DOI
10.1515/eletel-2017-0048
Publisher site
See Article on Publisher Site

Abstract

AbstractThis paper presents a ternary (4:2) compressor, which is an important component in multiplication. However, the structure differs from the binary counterpart since the ternary model does not require carry signals. The method of capacitive threshold logic (CTL) is used to achieve the output signals directly. Unlike the previously presented similar structure, the entire capacitor network is divided into two parts. This segregation results in higher reliability and robustness against unwanted process, voltage, and temperature (PVT) variations. Simulations are performed by HSPICE and 32nm CNFET technology. Simulation results demonstrate about 94% higher performance in terms of power-delay product (PDP) for the new design over the previous one.

Journal

International Journal of Electronics and Telecommunications – de Gruyter

Published: Nov 27, 2017

There are no references for this article.