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AbstractIn this paper a modified signal feed-through pulsed flip-flop has been presented for low power applications. Signal feed-through flip-flop uses a pass transistor to feed input data directly to the output. Feed through transistor and feedback signals have been modified for delay, static and dynamic power reduction. HSPICE simulation shows 22% reduction in leakage power and 8% of dynamic power. Delay has been reduced by 14% using TSMC 90nm technology parameters. The proposed pulsed flip-flop has the lowest PDP (Power Delay Product) among other pulsed flip-flops discussed.
International Journal of Electronics and Telecommunications – de Gruyter
Published: Aug 28, 2017
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