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- Publisher
- Association for Computing Machinery
- Copyright
- Copyright © 2013 by ACM Inc.
- ISSN
- 1550-4832
- DOI
- 10.1145/2422094.2422102
- Publisher site
- See Article on Publisher Site
Abstract
Variability in Nanoscale Fabrics: Bottom-up Integrated Analysis and Mitigation1 PRITISH NARAYANAN and MICHAEL LEUCHTENBURG, University of Massachusetts Amherst JORGE KINA, University of California Los Angeles PRACHI JOSHI and PAVAN PANCHAPAKESHAN, University of Massachusetts Amherst CHI ON CHUI, University of California Los Angeles C. ANDRAS MORITZ, University of Massachusetts Amherst Emerging nanodevice-based architectures will be impacted by parameter variation in conjunction with high defect rates. Variations in key physical parameters are caused by manufacturing imprecision as well as fundamental atomic scale randomness. In this article, the impact of parameter variation on nanoscale computing fabrics is extensively studied through a novel integrated methodology across device, circuit and architectural levels. This integrated approach enables to study in detail the impact of physical parameter variation across all fabric layers. A final contribution of the article includes novel techniques to address this impact. The variability framework, while generic, is explored extensively on the Nanoscale Application Specific Integrated Circuits (NASICs) nanowire fabric. For variation of = 10 in key physical parameters, the on current is found to vary by up to 3.5X. Circuit-level delay shows up to 118% deviation from nominal. Monte Carlo simulations using an architectural simulator found 67% nanoprocessor chips to operate
Journal
ACM Journal on Emerging Technologies in Computing Systems (JETC) – Association for Computing Machinery
Published: Feb 1, 2013