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Understanding Reduced-Voltage Operation in Modern DRAM Devices: Experimental Characterization, Analysis, and Mechanisms

Understanding Reduced-Voltage Operation in Modern DRAM Devices: Experimental Characterization,... Understanding Reduced-Voltage Operation in Modern DRAM Devices: Experimental Characterization, Analysis, and Mechanisms KEVIN K. CHANG, A. GRAY YALIKÇI, and SAUGATA GHOSE, Carnegie Mellon University ADITYA AGRAWAL and NILADRISH CHATTERJEE, NVIDIA ABHIJITH KASHYAP, Carnegie Mellon University DONGHYUK LEE and MIKE O'CONNOR , NVIDIA HASAN HASSAN and ONUR MUTLU , ETH Zürich The energy consumption of DRAM is a critical concern in modern computing systems. Improvements in manufacturing process technology have allowed DRAM vendors to lower the DRAM supply voltage conservatively, which reduces some of the DRAM energy consumption. We would like to reduce the DRAM supply voltage more aggressively, to further reduce energy. Aggressive supply voltage reduction requires a thorough understanding of the effect voltage scaling has on DRAM access latency and DRAM reliability. In this paper, we take a comprehensive approach to understanding and exploiting the latency and reliability characteristics of modern DRAM when the supply voltage is lowered below the nominal voltage level specified by DRAM standards. Using an FPGA-based testing platform, we perform an experimental study of 124 real DDR3L (low-voltage) DRAM chips manufactured recently by three major DRAM vendors. We find that reducing the supply voltage below a certain point introduces bit errors in the http://www.deepdyve.com/assets/images/DeepDyve-Logo-lg.png Proceedings of the ACM on Measurement and Analysis of Computing Systems Association for Computing Machinery

Understanding Reduced-Voltage Operation in Modern DRAM Devices: Experimental Characterization, Analysis, and Mechanisms

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References (144)

Publisher
Association for Computing Machinery
Copyright
Copyright © 2017 by ACM Inc.
ISSN
2476-1249
DOI
10.1145/3084447
Publisher site
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Abstract

Understanding Reduced-Voltage Operation in Modern DRAM Devices: Experimental Characterization, Analysis, and Mechanisms KEVIN K. CHANG, A. GRAY YALIKÇI, and SAUGATA GHOSE, Carnegie Mellon University ADITYA AGRAWAL and NILADRISH CHATTERJEE, NVIDIA ABHIJITH KASHYAP, Carnegie Mellon University DONGHYUK LEE and MIKE O'CONNOR , NVIDIA HASAN HASSAN and ONUR MUTLU , ETH Zürich The energy consumption of DRAM is a critical concern in modern computing systems. Improvements in manufacturing process technology have allowed DRAM vendors to lower the DRAM supply voltage conservatively, which reduces some of the DRAM energy consumption. We would like to reduce the DRAM supply voltage more aggressively, to further reduce energy. Aggressive supply voltage reduction requires a thorough understanding of the effect voltage scaling has on DRAM access latency and DRAM reliability. In this paper, we take a comprehensive approach to understanding and exploiting the latency and reliability characteristics of modern DRAM when the supply voltage is lowered below the nominal voltage level specified by DRAM standards. Using an FPGA-based testing platform, we perform an experimental study of 124 real DDR3L (low-voltage) DRAM chips manufactured recently by three major DRAM vendors. We find that reducing the supply voltage below a certain point introduces bit errors in the

Journal

Proceedings of the ACM on Measurement and Analysis of Computing Systems – Association for Computing Machinery

Published: Jun 13, 2017

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