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Sys er: Actor-Based Formal Veri cation of SystemC NILOOFAR RAZAVI, RAZIEH BEHJATI, HAMIDEH SABOURI, EHSAN KHAMESPANAH and AMIN SHALI University of Tehran and MARJAN SIRJANI University of Tehran and Reykjavik University SystemC is a system-level modeling language that can be used effectively for hardware/software co-design. Since a major goal of SystemC is to enable veri cation at higher levels of abstraction, the tendency is now directing to introducing formal veri cation approaches for SystemC. In this article, we propose an approach for formal veri cation of SystemC designs, and provide the semantics of SystemC using Labeled Transition Systems (LTS) for this purpose. An actor-based language, Rebeca, is used as an intermediate language. SystemC designs are mapped to Rebeca models and then Rebeca veri cation toolset is used to verify LTL and CTL properties. To tackle the statespace explosion, Rebeca model checkers offer some reduction policies that make them appropriate for SystemC veri cation. The approach also bene ts from the modular veri cation and program slicing techniques applied on Rebeca models. To show the applicability of our approach, we veri ed a single-cycle MIPS design and two hardware/software co-designs. The results show that our approach can effectively be
ACM Transactions on Embedded Computing Systems (TECS) – Association for Computing Machinery
Published: Dec 1, 2010
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