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Stigmergy-Based Security for SoC Operations From Runtime Performance Degradation of SoC Components

Stigmergy-Based Security for SoC Operations From Runtime Performance Degradation of SoC Components The semiconductor design industry of the embedded era has embraced the globalization strategy for system on chip (SoC) design. This involves incorporation of various SoC components or intellectual properties (IPs), procured from various third-party IP (3PIP) vendors. However, trust of an SoC is challenged when a supplied IP is counterfeit or implanted with a Hardware Trojan Horse. Both roots of untrust may result in sudden performance degradation at runtime. None of the existing hardware security approaches organize the behavior of the IPs at the low level, to ensure timely completion of SoC operations. However, real-time SoC operations are always associated with a deadline, and a deadline miss due to sudden performance degradation of any of the IPs may jeopardize mission-critical applications. We seek refuge to the stigmergic behavior exhibited in insect colonies to propose a decentralized self-aware security approach. The self-aware security modules attached with each IP works based on the Observe-Decide-Act paradigm and not only detects vulnerability but also organizes behavior of the IPs dynamically at runtime so that the high-level objective of task completion before a deadline is ensured. Experimental validation and low overhead of our proposed security modules over various benchmark IPs and crypto SoCs depict the prospects of our proposed mechanism. http://www.deepdyve.com/assets/images/DeepDyve-Logo-lg.png ACM Transactions on Embedded Computing Systems (TECS) Association for Computing Machinery

Stigmergy-Based Security for SoC Operations From Runtime Performance Degradation of SoC Components

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Publisher
Association for Computing Machinery
Copyright
Copyright © 2019 ACM
ISSN
1539-9087
eISSN
1558-3465
DOI
10.1145/3301279
Publisher site
See Article on Publisher Site

Abstract

The semiconductor design industry of the embedded era has embraced the globalization strategy for system on chip (SoC) design. This involves incorporation of various SoC components or intellectual properties (IPs), procured from various third-party IP (3PIP) vendors. However, trust of an SoC is challenged when a supplied IP is counterfeit or implanted with a Hardware Trojan Horse. Both roots of untrust may result in sudden performance degradation at runtime. None of the existing hardware security approaches organize the behavior of the IPs at the low level, to ensure timely completion of SoC operations. However, real-time SoC operations are always associated with a deadline, and a deadline miss due to sudden performance degradation of any of the IPs may jeopardize mission-critical applications. We seek refuge to the stigmergic behavior exhibited in insect colonies to propose a decentralized self-aware security approach. The self-aware security modules attached with each IP works based on the Observe-Decide-Act paradigm and not only detects vulnerability but also organizes behavior of the IPs dynamically at runtime so that the high-level objective of task completion before a deadline is ensured. Experimental validation and low overhead of our proposed security modules over various benchmark IPs and crypto SoCs depict the prospects of our proposed mechanism.

Journal

ACM Transactions on Embedded Computing Systems (TECS) – Association for Computing Machinery

Published: Mar 18, 2019

Keywords: Hardware Trojan Horses (HTH)

References

  • System-level protection and hardware Trojan detection using weighted voting
    Amin, H. A. M.; Alkabani, Y.; Selim, G. M. I.
  • Hardware Trojan attacks: Threat analysis and countermeasures
    Bhunia, S.; Hsiao, M. S.; Banga, M.; Narasimhan, S.
  • Defense Science Board Task Force on High Performance Microchip Supply
    Board, Defense Science
  • New methods to color vertices of a graph
    Brelaz, D.
  • Self Organization in Biological Systems
    Camazine, S.; Deneubourg, J. L.; Franks, N. R.; Sneyd, J.; Theraulaz, G.; Bonabeau, E.
  • Reports of Counterfeit Parts Quadruple Since 2009, Challenging US Defense Industry and National Security
    Cassell, J.
  • HARPOON: An obfuscation-based SoC design methodology for hardware protection
    Chakraborty, R. S.; Bhunia, S.
  • Security against hardware Trojan attacks using key-based design obfuscation
    Chakraborty, R. S.; Bhunia, S.
  • MERO: A statistical approach for hardware Trojan detection
    Chakraborty, R. S.; Wolff, F.; Paul, S.; Papachristou, C.; Bhunia, S.
  • Semiconductor manufacturers’ efforts to improve trust in the electronic part supply chain
    Chatterjee, K.; Das, D.
  • Task Allocation in Ant Colonies
    Cornejo, A.; Dornhaus, A.; Lynch, N.; Nagpal, R.
  • High-level synthesis for run-time hardware Trojan detection and recovery
    Cui, X.; Ma, K.; Shi, L.; Wu, K.
  • Worst-case finish time analysis for DAG-based applications in the presence of transient faults
    Cui, X.; Wu, K.; Wei, T.; Sha, E. H.
  • Ant system: Optimization by a colony of cooperating agents
    Dorigo, M.; Maniezzo, V.; Colorni, A.
  • Why do not all workers work? Colony size and workload during emigrations in the ant Temnothorax albipennis
    Dornhaus, A.; Holley, J. A.; Pook, V. G.; Worswick, G.; Franks, N. R.
  • A binary particle swarm optimization approach to fault diagnosis in parallel and distributed systems
    Falcon, R.; Almeida, M.; Nayak, A.
  • Preventing fault attack on stream cipher using randomization
    Ghosh, S.; Chowdhury, D. R.
  • RTNA: Securing SOC architectures from confidentiality attacks at runtime using ART1 neural networks
    Guha, K.; Saha, D.; Chakrabarti, A.
  • Self aware SoC security to counteract delay inducing hardware trojans at runtime
    Guha, K.; Saha, D.; Chakrabarti, A.
  • Real-time SoC security against passive threats using crypsis behavior of Geckos
    Guha, K.; Saha, D.; Chakrabarti, A.
  • Counterfeit integrated circuits: Detection, avoidance, and the challenges ahead
    Guin, U.; DiMase, D.; Tehranipoor, M.
  • Stigmergy as a universal coordination Mechanism I
    Heylighen, F.
  • International Technology Roadmap for Semiconductors Report
    ITRS.,
  • On-chip silicon odometers for circuit aging characterization
    Keane, J.; Wang, X.; Jain, P.; Kim, C. H.
  • Particle swarm optimization
    Kennedy, J.; Eberhart, R.
  • Silicon odometer: An on-chip reliability monitor for measuring frequency degradation of digital circuits
    Kim, T. H.; Persaud, R.; Kim, C. H.
  • Shielding heterogeneous MPSoCs from untrustworthy 3PIPs through security-driven task scheduling
    Liu, C.; Rajendran, J.; Yang, C.; Karri, R.
  • Proof-carrying hardware intellectual property: A pathway to trusted module acquisition
    Love, E.; Jin, Y.; Makris, Y.
  • Dynamic evaluation of hardware trust
    McIntyre, D.; Wolff, F.; Papachristou, C.; Bhunia, S.; Weyer, D.
  • Hardware Trojan detection by multiple-parameter side-channel analysis
    Narasimhan, S.; Du, D.; Chakraborty, R. S.; Paul, S.; Wolff, F. G.; Papachristou, C. A.
  • OpenCore Projects (Crypto Core Benchmarks)
    Benchmarks, OpenCores
  • Bogus: Electronic manufacturing and consumers confront a rising tide of counterfeit electronics
    Pecht, M.; Tiku, S.
  • High-level synthesis for security and trust
    Rajendran, J.; Zhang, H.; Sinanoglu, O.; Karri, R.
  • Building trustworthy systems using untrusted components: A high-level synthesis approach
    Rajendran, J. J.; Sinanoglu, O.; Karri, R.
  • Cyberphysical-system-on-chip (CPSoC): A self-aware MPSoC paradigm with cross-layer virtual sensing and actuation
    Sarma, S.; Dutt, N.; Gupta, P.; Venkatasubramanian, N.; Nicolau, A.
  • TL-HLS: Methodology for low cost hardware Trojan security aware scheduling with optimal loop unrolling factor during high level synthesis
    Sengupta, A.; Bhadauria, S.; Mohanty, S. P.
  • Defect-oriented non-intrusive RF test using on-chip temperature sensors
    Stratigopoulos, H. G.; Mir, S.; Abdallah, L.; Altet, J.
  • Physical unclonable functions for device authentication and secret key generation
    Suh, G. E.; Devadas, S.
  • Adaptive generation of unique IDs for digital chips through analog excitation
    Suresh, C. K. H.; Ozev, S.; Sinanoglu, O.
  • Efficient detection of faulty nodes with Cuckoo search in T-diagnosable systems
    Teske, A.; Falcon, R.; Nayak, A.
  • Response threshold reinforcements and division of labour in insect societies
    Theraulaz, G.; Bonabeau,
  • Designing collective behavior in a termite inspired robot construction team
    Werfel, J.; Petersen, K.; Nagpal, R.
  • A clock sweeping technique for detecting hardware Trojans impacting circuits delay
    Xiao, K.; Zhang, X.; Tehranipoor, M.
  • ZynQ-7000 SoC Technical Reference Manual UG585
    Inc, Xilinx
  • Cuckoo search via levy flights
    Yang, X. S.; Deb, S.
  • Path-delay fingerprinting for identification of recovered ICs
    Zhang, X.; Xiao, K.; Tehranipoor, M.
  • SACCI: Scan-based characterization through clock phase sweep for counterfeit chip detection
    Zheng, Y.; Wang, X.; Bhunia, S.