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Deming Zhang, L. Zeng, Youguang Zhang, Weisheng Zhao, Jacques-Olivier Klein (2016)
Stochastic spintronic device based synapses and spiking neurons for neuromorphic computation2016 IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH)
T. Stewart, Feng-Xuan Choo, C. Eliasmith (2012)
Spaun: A Perception-Cognition-Action Model Using Spiking NeuronsCognitive Science, 34
Trevor Bekolay, J. Bergstra, Eric Hunsberger, Travis DeWolf, T. Stewart, Daniel Rasmussen, Feng-Xuan Choo, Aaron Voelker, C. Eliasmith (2014)
Nengo: a Python tool for building large-scale functional brain modelsFrontiers in Neuroinformatics, 7
Masoud Zabihi, Z. Chowdhury, Zhengyang Zhao, Ulya Karpuzcu, Jianping Wang, S. Sapatnekar (2019)
In-Memory Processing on the Spintronic CRAM: From Hardware Design to Application MappingIEEE Transactions on Computers, 68
R. Lent, Frederico Azevedo, C. Andrade-Moraes, Ana Pinto (2012)
How many neurons do you have? Some dogmas of quantitative neuroscience under revisionEuropean Journal of Neuroscience, 35
G. NaveenMurali, F. Lalchhandama, K. Datta, I. Sengupta (2018)
Modelling and Simulation of Non-Ideal MAGIC NOR Gates on Memristor Crossbar2018 8th International Symposium on Embedded Computing and System Design (ISED)
Z. Chowdhury, S. Khatamifard, Zhengyang Zhao, Masoud Zabihi, Salonik Resch, Meisam Razaviyayn, Jianping Wang, S. Sapatnekar, Ulya Karpuzcu (2019)
Spintronic In-Memory Pattern MatchingIEEE Journal on Exploratory Solid-State Computational Devices and Circuits, 5
Andrew Lines, Prasad Joshi, Ruokun Liu, Steve McCoy, Jonathan Tse, Y. Weng, Mike Davies (2018)
Loihi Asynchronous Neuromorphic Research Chip2018 24th IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC)
Hiroki Noguchi, Kazutaka Ikegami, Keiichi Kushida, Keiko Abe, Shogo Itai, Satoshi Takaya, Naoharu Shimomura, et al (2015)
7Proceedings of the 2015 IEEE International Solid-State Circuits Conference (ISSCC’15): Digest of Technical Papers. IEEE, 2015
H. Markram (2012)
The human brain project.Scientific American, 306 6
S. Furber, F. Galluppi, S. Temple, L. Plana (2014)
The SpiNNaker ProjectProceedings of the IEEE, 102
R. Sabbaghi‐Nadooshan, M. Modarressi, H. Sarbazi-Azad (2008)
The 2D DBM: An attractive alternative to the simple 2D mesh topology for on-chip networks2008 IEEE International Conference on Computer Design
C. Frenkel, J. Legat, D. Bol (2018)
A 0.086-mm2 9.8-pJ/SOP 64k-Synapse 256-Neuron Online-Learning Digital Spiking Neuromorphic Processor in 28nm CMOSArXiv, abs/1804.07858
Mike Davies, N. Srinivasa, Tsung-Han Lin, G. Chinya, Yongqiang Cao, S. Choday, G. Dimou, Prasad Joshi, N. Imam, Shweta Jain, Yuyun Liao, Chit-Kwan Lin, Andrew Lines, Ruokun Liu, D. Mathaikutty, Steve McCoy, Arnab Paul, Jonathan Tse, Guruguhanathan Venkataramanan, Y. Weng, Andreas Wild, Yoonseok Yang, Hong Wang (2018)
Loihi: A Neuromorphic Manycore Processor with On-Chip LearningIEEE Micro, 38
Mohammad Hosseinabady, Mohammad Reza Kakoee, Jimson Mathew, Dhiraj K. Pradhan (2008)
De Bruijn graph as a low latency scalable architecture for energy efficient massive NoCsProceedings of the 2008 Conference on Design, 2008
Jianping Wang, S. Sapatnekar, C. Kim, P. Crowell, S. Koester, S. Datta, K. Roy, A. Raghunathan, X. Hu, M. Niemier, A. Naeemi, C. Chien, C. Ross, R. Kawakami (2017)
A Pathway to Enable Exponential Scaling for the Beyond-CMOS Era: InvitedProceedings of the 54th Annual Design Automation Conference 2017
Aayush Ankit, Abhronil Sengupta, P. Panda, K. Roy (2017)
RESPARC: A reconfigurable and energy-efficient architecture with Memristive Crossbars for deep Spiking Neural Networks2017 54th ACM/EDAC/IEEE Design Automation Conference (DAC)
H. Noguchi, K. Ikegami, K. Kushida, K. Abe, S. Itai, S. Takaya, N. Shimomura, J. Ito, A. Kawasumi, H. Hara, S. Fujita (2015)
7.5 A 3.3ns-access-time 71.2μW/MHz 1Mb embedded STT-MRAM using physically eliminated read-disturb scheme and normally-off memory architecture2015 IEEE International Solid-State Circuits Conference - (ISSCC) Digest of Technical Papers
Manuscript submitted to
Reza Sabbaghi-Nadooshan, Mehdi Modarressi, Hamid Sarbazi-Azad (2008)
The 2D DBM: An attractive alternative to the simple 2D mesh topology for on-chip networksProceedings of the 2008 IEEE International Conference on Computer Design. IEEE, 2008
G. Srinivasan, P. Panda, K. Roy (2018)
STDP-based Unsupervised Feature Learning using Convolution-over-time in Spiking Neural Networks for Energy-Efficient Neuromorphic ComputingACM Journal on Emerging Technologies in Computing Systems (JETC), 14
Yu Pan, P. Ouyang, Yinglin Zhao, W. Kang, S. Yin, Youguang Zhang, Weisheng Zhao, Shaojun Wei (2018)
A Multilevel Cell STT-MRAM-Based Computing In-Memory Accelerator for Binary Convolutional Neural NetworkIEEE Transactions on Magnetics, 54
Jian-Ping Wang, Sachin S. Sapatnekar, Chris H. Kim, Paul Crowell, Steve Koester, Supriyo Datta, Kaushik Roy, et al (2017)
A pathway to enable exponential scaling for the beyond-CMOS eraProceedings of the 54th Annual Design Automation Conference
E. Painkras, L. Plana, J. Garside, S. Temple, F. Galluppi, Cameron Patterson, D. Lester, A. Brown, S. Furber (2013)
SpiNNaker: A 1-W 18-Core System-on-Chip for Massively-Parallel Neural Network SimulationIEEE Journal of Solid-State Circuits, 48
D. Nikonov, I. Young (2019)
Benchmarking Delay and Energy of Neural Inference CircuitsIEEE Journal on Exploratory Solid-State Computational Devices and Circuits, 5
Evangelos Stromatias, Miguel Soto, T. Serrano-Gotarredona, B. Linares-Barranco (2017)
An Event-Driven Classifier for Spiking Neural Networks Fed with Synthetic or Dynamic Vision Sensor DataFrontiers in Neuroscience, 11
Terrence Stewart, Feng-Xuan Choo, Chris Eliasmith (2012)
Spaun: A perception-cognition-action model using spiking neuronsProceedings of the Annual Meeting of the Cognitive Science Society
An Inference and Learning Engine for Spiking Neural Networks in Computational RAM (CRAM)
Z. Chowdhury, J. Harms, S. Khatamifard, Masoud Zabihi, Yang Lv, A. Lyle, S. Sapatnekar, Ulya Karpuzcu, Jianping Wang (2018)
Efficient In-Memory Processing Using SpintronicsIEEE Computer Architecture Letters, 17
Kezhou Yang, Akul Malhotra, Sen Lu, Abhronil Sengupta (2019)
All-Spin Bayesian Neural NetworksIEEE Transactions on Electron Devices, 67
Shruti Kulkarni, Deepak Kadetotad, Shihui Yin, Jae-sun Seo, B. Rajendran (2019)
Neuromorphic Hardware Accelerator for SNN Inference based on STT-RAM Crossbar Arrays2019 26th IEEE International Conference on Electronics, Circuits and Systems (ICECS)
Liu, Kyungsook Lee
International Conference on Parallel Processing Optimal Routing Algorithms for Generalized de Bruijn Digraphs *
J. Dethier, P. Nuyujukian, C. Eliasmith, T. Stewart, Shauki Elasaad, K. Shenoy, K. Boahen (2011)
A Brain-Machine Interface Operating with a Real-Time Spiking Neural Network Control AlgorithmAdvances in neural information processing systems, 2011
Guoping Liu, Kyungsook Y. Lee (1993)
Optimal routing algorithms for generalized De Bruijn digraphsProceedings of the 1993 International Conference on Parallel Processing (ICPP’93), 1993
D. Saida, S. Kashiwada, Megumi Yakabe, T. Daibou, Naoki Hase, M. Fukumoto, S. Miwa, Yoshishige Suzuki, H. Noguchi, S. Fujita, J. Ito (2016)
Sub-3 ns pulse with sub-100 µA switching of 1x–2x nm perpendicular MTJ for high-performance embedded STT-MRAM towards sub-20 nm CMOS2016 IEEE Symposium on VLSI Technology
Shahar Kvatinsky, Dmitry Belousov, Slavik Liman, Guy Satat, Nimrod Wald, E. Friedman, A. Kolodny, U. Weiser (2014)
MAGIC—Memristor-Aided LogicIEEE Transactions on Circuits and Systems II: Express Briefs, 61
Peyman Faizian, Md Mollah, Xin Yuan, Zaid Alzaid, S. Pakin, M. Lang (2016)
Random Regular Graph and Generalized De Bruijn Graph with $k$ -Shortest Path RoutingIEEE Transactions on Parallel and Distributed Systems, 29
Xin Jin, M. Luján, L. Plana, Sergio Davies, S. Temple, S. Furber (2010)
Modeling Spiking Neural Networks on SpiNNakerComputing in Science & Engineering, 12
Sangho Chae, Jong Kim, Dongseung Kim, S. Hong, Sunggu Lee (1995)
DTN: A New Partitionable Torus Topology
Saransh Gupta, M. Imani, Tajana Simunic (2019)
Exploring Processing In-Memory for Different TechnologiesProceedings of the 2019 on Great Lakes Symposium on VLSI
Salonik Resch, S. Khatamifard, Z. Chowdhury, Masoud Zabihi, Zhengyang Zhao, Jianping Wang, S. Sapatnekar, Ulya Karpuzcu (2018)
PIMBALL: Binary Neural Networks in Spintronic MemoryACM Trans. Archit. Code Optim., 16
Shaahin Angizi, Jiao-Jin Sun, Wei Zhang, Deliang Fan (2019)
GraphS: A Graph Processing Accelerator Leveraging SOT-MRAM2019 Design, Automation & Test in Europe Conference & Exhibition (DATE)
Mei-Chin Chen, Abhronil Sengupta, K. Roy (2018)
Magnetic Skyrmion as a Spintronic Deep Learning Spiking Neuron ProcessorIEEE Transactions on Magnetics, 54
R. Singleton (1967)
A method for computing the fast Fourier transform with auxiliary memory and limited high-speed storageIEEE Transactions on Audio and Electroacoustics, 15
Shunti Yin, Deepak Kadetotad, Bonan Yan, Chang Song, Yiran Chen, C. Chakrabarti, Jae-sun Seo (2017)
Low-power neuromorphic speech recognition engine with coarse-grain sparsity2017 22nd Asia and South Pacific Design Automation Conference (ASP-DAC)
Sebastian Schmitt, Johann Klaehn, G. Bellec, Andreas Grübl, Maurice Guettler, Andreas Hartel, S. Hartmann, Dan Oliveira, Kai Husmann, V. Karasenko, Mitja Kleider, Christoph Koke, Christian Mauch, Eric Müller, Paul Müller, J. Partzsch, M. Petrovici, S. Schiefer, Stefan Scholze, B. Vogginger, R. Legenstein, W. Maass, C. Mayr, J. Schemmel, K. Meier (2017)
Neuromorphic hardware in the loop: Training a deep spiking network on the BrainScaleS wafer-scale system2017 International Joint Conference on Neural Networks (IJCNN)
Daisuke Saida, Saori Kashiwada, Megumi Yakabe, Tadaomi Daibou, Naoki Hase, Miyoshi Fukumoto, Shinji Miwa, et al (2016)
Sub-3 ns pulse with sub-100 A switching of 1x–2x nm perpendicular MTJ for high-performance embedded STT-MRAM towards sub-20 nm CMOSProceedings of the 2016 IEEE Symposium on VLSI Technology. IEEE, 2016
E. Vatajelu, L. Anghel (2017)
Fully-connected single-layer STT-MTJ-based spiking neural network under process variability2017 IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH)
(2015)
General structure for computational random access memory (CRAM)
K. Dang, B. Abderazek (2019)
An Efficient Software-Hardware Design Framework for Spiking Neural Network Systems2019 International Conference on Internet of Things, Embedded Systems and Communications (IINTEC)
G. Jan, L. Thomas, S. Le, Yuan-Jen Lee, Huanlong Liu, Jian Zhu, R. Tong, K. Pi, Yu-Jen Wang, D. Shen, R. He, J. Haq, J. Teng, V. Lam, K. Huang, T. Zhong, T. Torng, P. Wang (2014)
Demonstration of fully functional 8Mb perpendicular STT-MRAM chips with sub-5ns writing for non-volatile embedded memories2014 Symposium on VLSI Technology (VLSI-Technology): Digest of Technical Papers
Dayeol Lee, Gwangmu Lee, Dongup Kwon, Sunghwa Lee, Youngsok Kim, Jangwoo Kim (2018)
Flexon: A Flexible Digital Neuron for Efficient Spiking Neural Network Simulations2018 ACM/IEEE 45th Annual International Symposium on Computer Architecture (ISCA)
Abhronil Sengupta, Aparajita Banerjee, K. Roy (2015)
Hybrid Spintronic-CMOS Spiking Neural Network With On-Chip Learning: Devices, Circuits and SystemsArXiv, abs/1510.00432
A. Babu, O. Simeone, B. Rajendran (2020)
SpinAPS: A High-Performance Spintronic Accelerator for Probabilistic Spiking Neural NetworksArXiv, abs/2008.02189
Surya Narayanan, Karl Taht, R. Balasubramonian, Edouard Giacomin, P. Gaillardon (2020)
SpinalFlow: An Architecture and Dataflow Tailored for Spiking Neural Networks2020 ACM/IEEE 47th Annual International Symposium on Computer Architecture (ISCA)
Mohammad Hosseinabady, M. Kakoee, J. Mathew, D. Pradhan (2008)
De Bruijn Graph as a Low Latency Scalable Architecture for Energy Efficient Massive NoCs2008 Design, Automation and Test in Europe
Charlotte Frenkel, Martin Lefebvre, Jean-Didier Legat, David Bol (2018)
A 0IEEE Transactions on Biomedical Circuits and Systems, 13
D. Reis, M. Niemier, X. Hu (2018)
Computing in memory with FeFETsProceedings of the International Symposium on Low Power Electronics and Design
de Bruijn (1946)
A combinatorial problem, 49
Masoud Zabihi, Zhengyang Zhao, D. Mahendra, Z. Chowdhury, Salonik Resch, Thomas Peterson, Ulya Karpuzcu, Jianping Wang, S. Sapatnekar (2019)
Using Spin-Hall MTJs to Build an Energy-Efficient In-memory Computation Platform20th International Symposium on Quality Electronic Design (ISQED)
C. Frenkel, M. Lefebvre, J. Legat, D. Bol (2018)
A 0.086-mm$^2$ 12.7-pJ/SOP 64k-Synapse 256-Neuron Online-Learning Digital Spiking Neuromorphic Processor in 28-nm CMOSIEEE Transactions on Biomedical Circuits and Systems, 13
Salonik Resch, S. Khatamifard, Z. Chowdhury, Masoud Zabihi, Zhengyang Zhao, Hüsrev Cılasun, Jianping Wang, S. Sapatnekar, Ulya Karpuzcu (2020)
MOUSE: Inference In Non-volatile Memory for Energy Harvesting Applications2020 53rd Annual IEEE/ACM International Symposium on Microarchitecture (MICRO)
P. Merolla, J. Arthur, Rodrigo Alvarez-Icaza, A. Cassidy, J. Sawada, Filipp Akopyan, Bryan Jackson, N. Imam, Chen Guo, Yutaka Nakamura, B. Brezzo, I. Vo, Steven Esser, R. Appuswamy, B. Taba, A. Amir, M. Flickner, W. Risk, R. Manohar, D. Modha (2014)
A million spiking-neuron integrated circuit with a scalable communication network and interfaceScience, 345
Xiangyu Dong, Cong Xu, Yuan Xie, N. Jouppi (2012)
NVSim: A Circuit-Level Performance, Energy, and Area Model for Emerging Nonvolatile MemoryIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 31
P. Diehl, Matthew Cook (2015)
Unsupervised learning of digit recognition using spike-timing-dependent plasticityFrontiers in Computational Neuroscience, 9
Spiking Neural Networks (SNNs) represent a biologically inspired computation model capable of emulating neural computation in human brain and brain-like structures. The main promise is very low energy consumption. Classic Von Neumann architecture based SNN accelerators in hardware, however, often fall short of addressing demanding computation and data transfer requirements efficiently at scale. In this article, we propose a promising alternative to overcome scalability limitations, based on a network of in-memory SNN accelerators, which can reduce the energy consumption by up to 150.25= when compared to a representative ASIC solution. The significant reduction in energy comes from two key aspects of the hardware design to minimize data communication overheads: (1) each node represents an in-memory SNN accelerator based on a spintronic Computational RAM array, and (2) a novel, De Bruijn graph based architecture establishes the SNN array connectivity.
ACM Transactions on Architecture and Code Optimization (TACO) – Association for Computing Machinery
Published: Sep 29, 2021
Keywords: Processing in memory
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