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Reversible Synthesis of Symmetric Functions with a Simple Regular Structure and Easy Testability ARIGHNA DEB, Institute of Computer Science, University of Bremen DEBESH K. DAS, Computer Science and Engineering, Jadavpur University HAFIZUR RAHAMAN, Information Technology, Indian Institute of Engineering Science and Technology ROBERT WILLE, Institute for Integrated Circuits, Johannes Kepler University, Linz, Austria Cyber-Physical Systems, DFKI GmbH, Bremen, Germany ROLF DRECHSLER, Institute of Computer Science, University of Bremen, Bremen, Germany Cyber-Physical Systems, DFKI GmbH, Bremen, Germany BHARGAB B. BHATTACHARYA, Nanotechnology Research Triangle, Indian Statistical Institute In this article, we introduce a novel method of synthesizing symmetric Boolean functions with reversible logic gates. In contrast to earlier approaches, the proposed technique deploys a simple, regular, and cascaded structure consisting of an array of Peres and CNOT gates, which results in significant reduction with respect to the quantum cost. However, the number of circuit inputs may increase slightly when such cascades are used. In order to reduce their number, we next propose a postsynthesis optimization phase that allows judicious reuse of circuit lines. In addition to offering a cost-effective synthesis methodology, the proposed reversible logic structure supports elegant testability properties. With respect to all single or partial missing gate faults
ACM Journal on Emerging Technologies in Computing Systems (JETC) – Association for Computing Machinery
Published: Jun 27, 2016
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