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Register coalescing techniques for heterogeneous register architecture with copy sifting

Register coalescing techniques for heterogeneous register architecture with copy sifting Register Coalescing Techniques for Heterogeneous Register Architecture with Copy Sifting MINWOOK AHN and YUNHEUNG PAEK Seoul National University Optimistic coalescing has been proven as an elegant and effective technique that provides better chances of safely coloring more registers in register allocation than other coalescing techniques. Its algorithm originally assumes homogeneous registers, which are all gathered in the same register le. Although this register architecture is still common in most general-purpose processors, embedded processors often contain heterogeneous registers, which are scattered in physically different register les dedicated for each dissimilar purpose and use. In this work, we show that optimistic coalescing is also useful for an embedded processor to better handle such heterogeneity of the register architecture, and developed a modi ed algorithm for optimal coalescing that helps a register allocator. In the experiment, an existing register allocator was able to achieve up to 13.0% reduction in code size through our coalescing, and avoid many spills that would have been generated without our scheme. Categories and Subject Descriptors: D.3.4 [Programming Languages]: Processors ”Code generation, compiler and optimization General Terms: Algorithms, Performance, Design, Experimentation Additional Key Words and Phrases: Register allocation, register coalescing, compiler, embedded processors, heterogeneous register architecture Part http://www.deepdyve.com/assets/images/DeepDyve-Logo-lg.png ACM Transactions on Embedded Computing Systems (TECS) Association for Computing Machinery

Register coalescing techniques for heterogeneous register architecture with copy sifting

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References (23)

Publisher
Association for Computing Machinery
Copyright
Copyright © 2009 by ACM Inc.
ISSN
1539-9087
DOI
10.1145/1457255.1457263
Publisher site
See Article on Publisher Site

Abstract

Register Coalescing Techniques for Heterogeneous Register Architecture with Copy Sifting MINWOOK AHN and YUNHEUNG PAEK Seoul National University Optimistic coalescing has been proven as an elegant and effective technique that provides better chances of safely coloring more registers in register allocation than other coalescing techniques. Its algorithm originally assumes homogeneous registers, which are all gathered in the same register le. Although this register architecture is still common in most general-purpose processors, embedded processors often contain heterogeneous registers, which are scattered in physically different register les dedicated for each dissimilar purpose and use. In this work, we show that optimistic coalescing is also useful for an embedded processor to better handle such heterogeneity of the register architecture, and developed a modi ed algorithm for optimal coalescing that helps a register allocator. In the experiment, an existing register allocator was able to achieve up to 13.0% reduction in code size through our coalescing, and avoid many spills that would have been generated without our scheme. Categories and Subject Descriptors: D.3.4 [Programming Languages]: Processors ”Code generation, compiler and optimization General Terms: Algorithms, Performance, Design, Experimentation Additional Key Words and Phrases: Register allocation, register coalescing, compiler, embedded processors, heterogeneous register architecture Part

Journal

ACM Transactions on Embedded Computing Systems (TECS) – Association for Computing Machinery

Published: Jan 1, 2009

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