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- Publisher
- Association for Computing Machinery
- Copyright
- Copyright © 2010 by ACM Inc.
- ISSN
- 1539-9087
- DOI
- 10.1145/1880050.1880061
- Publisher site
- See Article on Publisher Site
Abstract
Parametric Timing Analysis and Its Application to Dynamic Voltage Scaling SIBIN MOHAN and FRANK MUELLER North Carolina State University MICHAEL ROOT, WILLIAM HAWKINS, and CHRISTOPHER HEALY Furman University DAVID WHALLEY Florida State University and EMILIO VIVANCOS Universidad Politecnica de Valencia Embedded systems with real-time constraints depend on a priori knowledge of worst-case execution times (WCETs) to determine if tasks meet deadlines. Static timing analysis derives bounds on WCETs but requires statically known loop bounds. This work removes the constraint on known loop bounds through parametric analysis expressing WCETs as functions. Tighter WCETs are dynamically discovered to exploit slack by dynamic voltage scaling (DVS) saving 60% to 82% energy over DVS-oblivious techniques and showing savings close to more costly dynamic-priority DVS algorithms. Overall, parametric analysis expands the class of real-time applications to programs with loopinvariant dynamic loop bounds while retaining tight WCET bounds. Categories and Subject Descriptors: D.4.1 [Operating Systems]: Process Management ”Scheduling; D.4.7 [Operating Systems]: Organization and Design ”Real-time systems and embedded systems This work was conducted at North Carolina State University and Florida State University; it was supported in part by NSF grants CCR-0208581, CCR-0310860, CCR-0312695, EIA-0072043, CCR-0208892, CCR-0312493 and CCR-0312531. Author ™s addresses: S. Mohan and
Journal
ACM Transactions on Embedded Computing Systems (TECS) – Association for Computing Machinery
Published: Dec 1, 2010