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Parallelizing the Chambolle Algorithm for Performance-Optimized Mapping on FPGA Devices ´ IVAN BERETTA, Ecole Polytechnique F´ d´ rale de Lausanne e e VINCENZO RANA, Politecnico di Milano ´ ABDULKADIR AKIN, Ecole Polytechnique F´ d´ rale de Lausanne e e ALESSANDRO ANTONIO NACCI and DONATELLA SCIUTO, Politecnico di Milano ´ DAVID ATIENZA, Ecole Polytechnique F´ d´ rale de Lausanne e e The performance and the efficiency of recent computing platforms have been deeply influenced by the widespread adoption of hardware accelerators, such as graphics processing units (GPUs) or fieldprogrammable gate arrays (FPGAs), which are often employed to support the tasks of general-purpose processors (GPPs). One of the main advantages of these accelerators over their sequential counterparts (GPPs) is their ability to perform massive parallel computation. However, to exploit this competitive edge, it is necessary to extract the parallelism from the target algorithm to be executed, which generally is a very challenging task. This concept is demonstrated, for instance, by the poor performance achieved on relevant multimedia algorithms, such as Chambolle, which is a well-known algorithm employed for the optical flow estimation. The implementations of this algorithm that can be found in the state of the art are generally based
ACM Transactions on Embedded Computing Systems (TECS) – Association for Computing Machinery
Published: Mar 7, 2016
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