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On-Chip Caches Built on Multilevel Spin-Transfer Torque RAM Cells and Its Optimizations YIRAN CHEN, University of Pittsburgh WENG-FAI WONG, National University of Singapore HAI LI, Polytechnic Institute of New York University CHENG-KOK KOH, Purdue University YAOJUN ZHANG and WUJIE WEN, University of Pittsburgh It has been predicted that a processor's caches could occupy as much as 90% of chip area a few technology nodes from the current ones. In this article, we investigate the use of multilevel spin-transfer torque RAM (STT-RAM) cells in the design of processor caches. We start with examining the access (read and write) scheme for multilevel cell (MLC) STT-RAM from a circuit design perspective, detailing the read and write circuits. Compared to traditional SRAM caches, a multilevel cell (MLC) STT-RAM cache design is denser, fast, and requires less energy. However, a number of critical architecture-level issues remain to be solved before MLC STT-RAM technology can be deployed in processor caches. We shall offer solutions to the issue of bit encoding as well as tackle the write endurance problem. In particular, the latter has been neglected in previous works on STT-RAM caches. We propose a set remapping scheme that can potentially prolong the lifetime of
ACM Journal on Emerging Technologies in Computing Systems (JETC) – Association for Computing Machinery
Published: May 1, 2013
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