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NoC contention analysis using a branch-and-prune algorithm

NoC contention analysis using a branch-and-prune algorithm NoC Contention Analysis Using a Branch-and-Prune Algorithm ´ ´ DAKSHINA DASARI, BORISLAV NIKOLIC, VINCENT NELIS, and STEFAN M. PETTERS, CISTER/INESC-TEC Research Center, Polytechnic Institute of Porto "Many-core" systems based on a Network-on-Chip (NoC) architecture offer various opportunities in terms of performance and computing capabilities, but at the same time they pose many challenges for the deployment of real-time systems, which must fulfill specific timing requirements at runtime. It is therefore essential to identify, at design time, the parameters that have an impact on the execution time of the tasks deployed on these systems and the upper bounds on the other key parameters. The focus of this work is to determine an upper bound on the traversal time of a packet when it is transmitted over the NoC infrastructure. Towards this aim, we first identify and explore some limitations in the existing recursive-calculus-based approaches to compute the Worst-Case Traversal Time (WCTT) of a packet. Then, we extend the existing model by integrating the characteristics of the tasks that generate the packets. For this extended model, we propose an algorithm called "Branch and Prune" (BP). Our proposed method provides tighter and safe estimates than the existing recursive-calculus-based approaches. Finally, we http://www.deepdyve.com/assets/images/DeepDyve-Logo-lg.png ACM Transactions on Embedded Computing Systems (TECS) Association for Computing Machinery

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References (28)

Publisher
Association for Computing Machinery
Copyright
Copyright © 2014 by ACM Inc.
ISSN
1539-9087
DOI
10.1145/2567937
Publisher site
See Article on Publisher Site

Abstract

NoC Contention Analysis Using a Branch-and-Prune Algorithm ´ ´ DAKSHINA DASARI, BORISLAV NIKOLIC, VINCENT NELIS, and STEFAN M. PETTERS, CISTER/INESC-TEC Research Center, Polytechnic Institute of Porto "Many-core" systems based on a Network-on-Chip (NoC) architecture offer various opportunities in terms of performance and computing capabilities, but at the same time they pose many challenges for the deployment of real-time systems, which must fulfill specific timing requirements at runtime. It is therefore essential to identify, at design time, the parameters that have an impact on the execution time of the tasks deployed on these systems and the upper bounds on the other key parameters. The focus of this work is to determine an upper bound on the traversal time of a packet when it is transmitted over the NoC infrastructure. Towards this aim, we first identify and explore some limitations in the existing recursive-calculus-based approaches to compute the Worst-Case Traversal Time (WCTT) of a packet. Then, we extend the existing model by integrating the characteristics of the tasks that generate the packets. For this extended model, we propose an algorithm called "Branch and Prune" (BP). Our proposed method provides tighter and safe estimates than the existing recursive-calculus-based approaches. Finally, we

Journal

ACM Transactions on Embedded Computing Systems (TECS)Association for Computing Machinery

Published: Mar 1, 2014

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