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Modeling and optimizing run-time reconfiguration using evolutionary computation

Modeling and optimizing run-time reconfiguration using evolutionary computation Modeling and Optimizing Run-Time Recon guration Using Evolutionary Computation J. HARKIN, T. M. MCGINNITY, and L. P. MAGUIRE University of Ulster The hardware “software (HW “SW) partitioning of applications to dynamically recon gurable embedded systems allows for customization of their hardware resources during run-time to meet the demands of executing applications. The run-time recon guration (RTR) of such systems can have an impact on the HW “SW partitioning strategy and the system performance. It is therefore important to consider approaches to optimally reduce the RTR overhead during the HW “SW partitioning stage. In order to examine potential bene ts in performance, it is necessary to develop a method to model and evaluate the RTR. In this paper, a novel method of modeling and evaluating such RTR-reduced HW “SW partitions is presented. The techniques of computation-recon guration overlap and the retention of circuitry between recon gurations are used within this model to explore the possibilities of RTR reduction. The integration of this model into the authors ™ current genetic-algorithm-driven HW “SW partitioner is also presented, with two applications used to illustrate the bene ts of RTR-reduced exploration during HW “SW partitioning. Categories and Subject Descriptors: C.4 [Computer Systems Organization]: http://www.deepdyve.com/assets/images/DeepDyve-Logo-lg.png ACM Transactions on Embedded Computing Systems (TECS) Association for Computing Machinery

Modeling and optimizing run-time reconfiguration using evolutionary computation

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References (42)

Publisher
Association for Computing Machinery
Copyright
Copyright © 2004 by ACM Inc.
ISSN
1539-9087
DOI
10.1145/1027794.1027795
Publisher site
See Article on Publisher Site

Abstract

Modeling and Optimizing Run-Time Recon guration Using Evolutionary Computation J. HARKIN, T. M. MCGINNITY, and L. P. MAGUIRE University of Ulster The hardware “software (HW “SW) partitioning of applications to dynamically recon gurable embedded systems allows for customization of their hardware resources during run-time to meet the demands of executing applications. The run-time recon guration (RTR) of such systems can have an impact on the HW “SW partitioning strategy and the system performance. It is therefore important to consider approaches to optimally reduce the RTR overhead during the HW “SW partitioning stage. In order to examine potential bene ts in performance, it is necessary to develop a method to model and evaluate the RTR. In this paper, a novel method of modeling and evaluating such RTR-reduced HW “SW partitions is presented. The techniques of computation-recon guration overlap and the retention of circuitry between recon gurations are used within this model to explore the possibilities of RTR reduction. The integration of this model into the authors ™ current genetic-algorithm-driven HW “SW partitioner is also presented, with two applications used to illustrate the bene ts of RTR-reduced exploration during HW “SW partitioning. Categories and Subject Descriptors: C.4 [Computer Systems Organization]:

Journal

ACM Transactions on Embedded Computing Systems (TECS)Association for Computing Machinery

Published: Nov 1, 2004

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