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Modeling and design challenges and solutions for carbon nanotube-based interconnect in future high performance integrated circuits

Modeling and design challenges and solutions for carbon nanotube-based interconnect in future... Single-walled carbon nanotube (SWCNT) bundles have the potential to provide an attractive solution for the resistivity and electromigration problems faced by traditional copper interconnect as technology scales into the nanoscale regime. In this article, we evaluate the performance and reliability of nanotube bundles for both local and global interconnect in future VLSI applications. To provide a holistic evaluation of SWCNT bundles for on-chip interconnect, we have developed an efficient equivalent circuit model that captures the statistical distribution of individual metallic and semiconducting nanotubes while accurately incorporating recent experimental and theoretical results on inductance, contact resistance, and ohmic resistance. Leveraging the circuit model, we examine the performance and reliability of nanotube bundles for both individual signal lines and system-level designs. SWCNT interconnect bundles can provide significant improvement in delay and maximum current density over traditional copper interconnect, depending on bundle geometry and process technology. However, for system-level designs, the statistical variation in the delay of SWCNT bundles may lead to reliability issues in future process technology. Consequently, if the SWCNT chirality can be effectively controlled and other manufacturing challenges are met, SWCNT bundles potentially are a viable alternative to standard copper interconnect as process technology scales. http://www.deepdyve.com/assets/images/DeepDyve-Logo-lg.png ACM Journal on Emerging Technologies in Computing Systems (JETC) Association for Computing Machinery

Modeling and design challenges and solutions for carbon nanotube-based interconnect in future high performance integrated circuits

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Publisher
Association for Computing Machinery
Copyright
Copyright © 2006 by ACM Inc.
ISSN
1550-4832
DOI
10.1145/1167943.1167944
Publisher site
See Article on Publisher Site

Abstract

Single-walled carbon nanotube (SWCNT) bundles have the potential to provide an attractive solution for the resistivity and electromigration problems faced by traditional copper interconnect as technology scales into the nanoscale regime. In this article, we evaluate the performance and reliability of nanotube bundles for both local and global interconnect in future VLSI applications. To provide a holistic evaluation of SWCNT bundles for on-chip interconnect, we have developed an efficient equivalent circuit model that captures the statistical distribution of individual metallic and semiconducting nanotubes while accurately incorporating recent experimental and theoretical results on inductance, contact resistance, and ohmic resistance. Leveraging the circuit model, we examine the performance and reliability of nanotube bundles for both individual signal lines and system-level designs. SWCNT interconnect bundles can provide significant improvement in delay and maximum current density over traditional copper interconnect, depending on bundle geometry and process technology. However, for system-level designs, the statistical variation in the delay of SWCNT bundles may lead to reliability issues in future process technology. Consequently, if the SWCNT chirality can be effectively controlled and other manufacturing challenges are met, SWCNT bundles potentially are a viable alternative to standard copper interconnect as process technology scales.

Journal

ACM Journal on Emerging Technologies in Computing Systems (JETC)Association for Computing Machinery

Published: Jul 1, 2006

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