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Matrix Nanodevice-Based Logic Architectures and Associated Functional Mapping Method

Matrix Nanodevice-Based Logic Architectures and Associated Functional Mapping Method JET00003 ACM (Typeset by SPi, Manila, Philippines) 1 of 23 January 26, 2011 Matrix Nanodevice-Based Logic Architectures and Associated Functional Mapping Method P.-E. GAILLARDON and F. CLERMIDY, CEA, LETI, Minatec Campus I. O ™CONNOR and J. LIU, University of Lyon M. AMADOU and G. NICOLESCU, Ecole Polytechnique de Montr al e This article describes a novel computing architecture organization based on nanoscale logic cells. We propose the use of a cluster of matrix arrangements of cells. In order to interconnect such ne-grained logic cells within a matrix, conventional techniques are not suitable due to a large interconnect overhead. Therefore, we propose the use of static and incomplete interconnect topologies to create matrices of cells. We also propose a method to map functions onto such architectures. We then explore the main parameters of the structure (size of matrices and interconnect topologies) and their impact on the main performance metrics (packing ef ciency, speed, and fault tolerance). A cluster packing method also allows the evaluation of the number of matrices used by complex functions and the ll factor for various matrix sizes. The analyses show that this approach is particularly suited for matrices of 16 cells interconnected by modi ed http://www.deepdyve.com/assets/images/DeepDyve-Logo-lg.png ACM Journal on Emerging Technologies in Computing Systems (JETC) Association for Computing Machinery

Matrix Nanodevice-Based Logic Architectures and Associated Functional Mapping Method

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Publisher
Association for Computing Machinery
Copyright
Copyright © 2011 by ACM Inc.
ISSN
1550-4832
DOI
10.1145/1899390.1899393
Publisher site
See Article on Publisher Site

Abstract

JET00003 ACM (Typeset by SPi, Manila, Philippines) 1 of 23 January 26, 2011 Matrix Nanodevice-Based Logic Architectures and Associated Functional Mapping Method P.-E. GAILLARDON and F. CLERMIDY, CEA, LETI, Minatec Campus I. O ™CONNOR and J. LIU, University of Lyon M. AMADOU and G. NICOLESCU, Ecole Polytechnique de Montr al e This article describes a novel computing architecture organization based on nanoscale logic cells. We propose the use of a cluster of matrix arrangements of cells. In order to interconnect such ne-grained logic cells within a matrix, conventional techniques are not suitable due to a large interconnect overhead. Therefore, we propose the use of static and incomplete interconnect topologies to create matrices of cells. We also propose a method to map functions onto such architectures. We then explore the main parameters of the structure (size of matrices and interconnect topologies) and their impact on the main performance metrics (packing ef ciency, speed, and fault tolerance). A cluster packing method also allows the evaluation of the number of matrices used by complex functions and the ll factor for various matrix sizes. The analyses show that this approach is particularly suited for matrices of 16 cells interconnected by modi ed

Journal

ACM Journal on Emerging Technologies in Computing Systems (JETC) – Association for Computing Machinery

Published: Jan 1, 2011

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