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Numerous computing applications can tolerate low error rates. In such applications, inexact approaches provide the ability to achieve significantly lower power. This work demonstrates the power-error trade-offs that can be achieved. Using probabilistic modeling in sub-50-nm silicon transistor technology, the relationship between statistical uncertainties and errors are elucidated for different configurations and topologies and the trade-offs quantified. Gate-level implementation of the probabilistic CMOS logic is validated by circuit simulations of a commercial 45-nm SOI CMOS process technology. Using a practical ALU architecture where voltages can be scaled from most significant to least significant bit blocks as an example, the potential benefits of this technique are shown. A calculation error of 106, an error rate quite tolerable for many computational tasks, is shown to be possible with a total power reduction of more than 40.
ACM Journal on Emerging Technologies in Computing Systems (JETC) – Association for Computing Machinery
Published: Mar 6, 2014
Keywords: Energy-efficiency
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