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Guest Editors’ Introduction to the Special Section on Hardware and Algorithms for Energy-Constrained On-chip Machine Learning JAE-SUN SEO and YU CAO, Arizona State University XIN LI, Duke University PAUL WHATMOUGH, Arm Research Recently, machine/deep learning algorithms has unprecedentedly improved the accuracies in prac- tical recognition and classification tasks. However, to achieve incremental accuracy improvement, state-of-the-art deep neural network (DNN) algorithms tend to present very deep and large models, which pose significant challenges for custom hardware implementations in terms of computation, memory, and communication. This is especially true for energy-/resource-constrained hardware platforms (e.g., mobile/wearable devices, self-driving cars, IoT systems), where various constraints exist in power, performance, and area. There is a timely need to map the latest machine learning algorithms to application-specific hardware (e.g., ASIC, FPGA, emerging devices), in order to achieve orders of magnitude im- provement in performance, energy efficiency, and density. Recent progress in emerging hardware- friendly algorithms and nanoelectronic technology will further help shed light on future hardware- software platforms for on-chip learning. The objective of this special issue is to explore the potential of on-chip machine learning, to reveal emerging algorithms and design needs, and to promote novel applications for learning. A holistic approach of concurrent
ACM Journal on Emerging Technologies in Computing Systems (JETC) – Association for Computing Machinery
Published: May 31, 2019
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