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Guest editorial: IEEE/ACM symposium on nanoscale architectures (NANOARCH07)

Guest editorial: IEEE/ACM symposium on nanoscale architectures (NANOARCH07) Guest Editorial: IEEE/ACM Symposium on Nanoscale Architectures (NANOARCH07) As silicon technology is reaching the lower end of nanometer ranges of feature size (45nm CMOS technology is already in use), the continuation of Moore ™s law-based scaling of silicon technology is now facing several challenges. The reduced feature size implies a larger number of the transistors on the unit area of silicon chips which provides both scopes for newer features in our computation capabilities, coupled with the problem of increased defect rates and susceptibility to transient faults. Since defect rates can go up 10% or more, traditional discarding of silicon chips based on defects would reduce yields to such low levels that alternative measures of yield enhancements are imperative. One possible way is to enhance the computing logic and micro-architectures with defect- and fault-tolerance features that would make computation robust against such high level of defects and faults, hence increasing yields. On the other hand, engineers and scientists are now engaged in nding alternatives to silicon-based computing such that nanoscale computation can be realized with molecular dynamics, quantum effects, and other nontraditional material and computation paradigms. Molecular transistors, DNA-scaffoldingbased computation fabrics, carbon nanotube-based eld effect transistors, carbon nanotube-based PLA http://www.deepdyve.com/assets/images/DeepDyve-Logo-lg.png ACM Journal on Emerging Technologies in Computing Systems (JETC) Association for Computing Machinery

Guest editorial: IEEE/ACM symposium on nanoscale architectures (NANOARCH07)

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Publisher
Association for Computing Machinery
Copyright
Copyright © 2009 by ACM Inc.
ISSN
1550-4832
DOI
10.1145/1482613.1482614
Publisher site
See Article on Publisher Site

Abstract

Guest Editorial: IEEE/ACM Symposium on Nanoscale Architectures (NANOARCH07) As silicon technology is reaching the lower end of nanometer ranges of feature size (45nm CMOS technology is already in use), the continuation of Moore ™s law-based scaling of silicon technology is now facing several challenges. The reduced feature size implies a larger number of the transistors on the unit area of silicon chips which provides both scopes for newer features in our computation capabilities, coupled with the problem of increased defect rates and susceptibility to transient faults. Since defect rates can go up 10% or more, traditional discarding of silicon chips based on defects would reduce yields to such low levels that alternative measures of yield enhancements are imperative. One possible way is to enhance the computing logic and micro-architectures with defect- and fault-tolerance features that would make computation robust against such high level of defects and faults, hence increasing yields. On the other hand, engineers and scientists are now engaged in nding alternatives to silicon-based computing such that nanoscale computation can be realized with molecular dynamics, quantum effects, and other nontraditional material and computation paradigms. Molecular transistors, DNA-scaffoldingbased computation fabrics, carbon nanotube-based eld effect transistors, carbon nanotube-based PLA

Journal

ACM Journal on Emerging Technologies in Computing Systems (JETC) – Association for Computing Machinery

Published: Jan 1, 2009

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