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Gated-diode FinFET DRAMs: Device and circuit design-considerations

Gated-diode FinFET DRAMs: Device and circuit design-considerations Gated-Diode FinFET DRAMs: Device and Circuit Design-Considerations AJAY N. BHOJ and NIRAJ K. JHA Princeton University Scaling bulk CMOS SRAM technology for on-chip caches beyond the 22nm node is questionable, on account of high leakage power consumption, performance degradation, and instability due to process variations. Recently, two-three transistor one gated-diode (2T/3T1D) DRAMs were proposed as alternatives to address the SRAM variability problem, with an emphasis on highactivity embedded cache applications. They are highly competitive to SRAM in terms of performance, while having a smaller power and area footprint at lower technology nodes. The current evolutionary trend in transistor structures is moving toward an era of multigate devices, which makes it necessary to identify design issues and advantages of gated-diode DRAMs implemented in a multigate technology. In this work, we address gated-diode DRAM design in FinFET technology using mixed-mode 2D-device simulations. We revisit the model of internal voltage gain in bulk gated diodes and extend it to provide quantitative insight into designing Fin gated diodes, that is, gated diodes in FinFET technology. To this effect, we propose FinFET variants of the bulk gated-diode con guration and identify parameters that are critical to enhancing the retention time and read current http://www.deepdyve.com/assets/images/DeepDyve-Logo-lg.png ACM Journal on Emerging Technologies in Computing Systems (JETC) Association for Computing Machinery

Gated-diode FinFET DRAMs: Device and circuit design-considerations

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Publisher
Association for Computing Machinery
Copyright
Copyright © 2010 by ACM Inc.
ISSN
1550-4832
DOI
10.1145/1877745.1877746
Publisher site
See Article on Publisher Site

Abstract

Gated-Diode FinFET DRAMs: Device and Circuit Design-Considerations AJAY N. BHOJ and NIRAJ K. JHA Princeton University Scaling bulk CMOS SRAM technology for on-chip caches beyond the 22nm node is questionable, on account of high leakage power consumption, performance degradation, and instability due to process variations. Recently, two-three transistor one gated-diode (2T/3T1D) DRAMs were proposed as alternatives to address the SRAM variability problem, with an emphasis on highactivity embedded cache applications. They are highly competitive to SRAM in terms of performance, while having a smaller power and area footprint at lower technology nodes. The current evolutionary trend in transistor structures is moving toward an era of multigate devices, which makes it necessary to identify design issues and advantages of gated-diode DRAMs implemented in a multigate technology. In this work, we address gated-diode DRAM design in FinFET technology using mixed-mode 2D-device simulations. We revisit the model of internal voltage gain in bulk gated diodes and extend it to provide quantitative insight into designing Fin gated diodes, that is, gated diodes in FinFET technology. To this effect, we propose FinFET variants of the bulk gated-diode con guration and identify parameters that are critical to enhancing the retention time and read current

Journal

ACM Journal on Emerging Technologies in Computing Systems (JETC)Association for Computing Machinery

Published: Dec 1, 2010

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