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- Publisher
- Association for Computing Machinery
- Copyright
- Copyright © 2017 ACM
- ISSN
- 1539-9087
- eISSN
- 1558-3465
- DOI
- 10.1145/3126530
- Publisher site
- See Article on Publisher Site
Abstract
Modern multiprocessor systems-on-chip (MpSoCs) offer tremendous power and performance optimization opportunities by tuning thousands of potential voltage, frequency and core configurations. As the workload phases change at runtime, different configurations may become optimal with respect to power, performance or other metrics. Identifying the optimal configuration at runtime is infeasible due to the large number of workloads and configurations. This paper proposes a novel methodology that can find the Pareto-optimal configurations at runtime as a function of the workload. To achieve this, we perform an extensive offline characterization to find classifiers that map performance counters to optimal configurations. Then, we use these classifiers and performance counters at runtime to choose Pareto-optimal configurations. We evaluate the proposed methodology by maximizing the performance per watt for 18 single- and multi-threaded applications. Our experiments demonstrate an average increase of 93%, 81% and 6% in performance per watt compared to the interactive, ondemand and powersave governors, respectively.
Journal
ACM Transactions on Embedded Computing Systems (TECS) – Association for Computing Machinery
Published: Sep 27, 2017
Keywords: Basic blocks