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Design and Evaluation of Technology-Agnostic Heterogeneous Networks-on-Chip

Design and Evaluation of Technology-Agnostic Heterogeneous Networks-on-Chip Design and Evaluation of Technology-Agnostic Heterogeneous Networks-on-Chip HAERA CHUNG and CHRISTOF TEUSCHER, Portland State University PARTHA PANDE, Washington State University Traditional metal-wire-based networks-on-chip (NoC) suffer from high latency and power dissipation as the system size scales up in the number of cores. This limitation stems from the inherent multihop communication nature of larger NoCs. It has previously been shown that the performance of NoCs can be significantly improved by introducing long-range, low power, and high-bandwidth single-hop links between distant cores. While previous work has focused on specific NoC architectures and configurations, it remains an open question whether heterogeneous link types are beneficial in a broad range of NoC architectures. In this article, we show that a generic NoC architecture with heterogeneous link types allows for NoCs with higher bandwidth at a lower cost compared to homogeneous networks. We further show that such NoCs scale up significantly better in terms of performance and cost. We demonstrate these broadly-applicable results by using a technology-agnostic complex network approach that targets NoC architectures with various emerging link types. Categories and Subject Descriptors: C.2.2 [Computer-Communication Networks]: Network Protocols General Terms: Design, Algorithms, Performance Additional Key Words and Phrases: Networks-on-chip, heterogeneous, wireless, optical ACM http://www.deepdyve.com/assets/images/DeepDyve-Logo-lg.png ACM Journal on Emerging Technologies in Computing Systems (JETC) Association for Computing Machinery

Design and Evaluation of Technology-Agnostic Heterogeneous Networks-on-Chip

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Publisher
Association for Computing Machinery
Copyright
Copyright © 2014 by ACM Inc.
ISSN
1550-4832
DOI
10.1145/2567666
Publisher site
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Abstract

Design and Evaluation of Technology-Agnostic Heterogeneous Networks-on-Chip HAERA CHUNG and CHRISTOF TEUSCHER, Portland State University PARTHA PANDE, Washington State University Traditional metal-wire-based networks-on-chip (NoC) suffer from high latency and power dissipation as the system size scales up in the number of cores. This limitation stems from the inherent multihop communication nature of larger NoCs. It has previously been shown that the performance of NoCs can be significantly improved by introducing long-range, low power, and high-bandwidth single-hop links between distant cores. While previous work has focused on specific NoC architectures and configurations, it remains an open question whether heterogeneous link types are beneficial in a broad range of NoC architectures. In this article, we show that a generic NoC architecture with heterogeneous link types allows for NoCs with higher bandwidth at a lower cost compared to homogeneous networks. We further show that such NoCs scale up significantly better in terms of performance and cost. We demonstrate these broadly-applicable results by using a technology-agnostic complex network approach that targets NoC architectures with various emerging link types. Categories and Subject Descriptors: C.2.2 [Computer-Communication Networks]: Network Protocols General Terms: Design, Algorithms, Performance Additional Key Words and Phrases: Networks-on-chip, heterogeneous, wireless, optical ACM

Journal

ACM Journal on Emerging Technologies in Computing Systems (JETC) – Association for Computing Machinery

Published: Apr 1, 2014

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