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Design and evaluation of random linear network coding Accelerators on FPGAs

Design and evaluation of random linear network coding Accelerators on FPGAs Design and Evaluation of Random Linear Network Coding Accelerators on FPGAs SUNWOO KIM, Hyundai Motor Company WON SEOB JEONG and WON W. RO, Yonsei University JEAN-LUC GAUDIOT, University of California, Irvine Network coding is a well-known technique used to enhance network throughput and reliability by applying special coding to data packets. One critical problem in practice, when using the random linear network coding technique, is the high computational overhead. More specifically, using this technique in embedded systems with low computational power might cause serious delays due to the complex Galois field operations and matrix handling. To this end, this article proposes a high-performance decoding logic for random linear network coding using field-programmable gate-array (FPGA) technology. We expect that the inherent reconfigurability of FPGAs will provide sufficient performance as well as programmability to cope with changes in the specification of the coding. The main design motivation was to improve the decoding delay by dividing and parallelizing the entire decoding process. Fast arithmetic operations are achieved by the proposed parallelized GF ALUs, which allow calculations with all the elements of a single row of a matrix to be performed concurrently. To improve the flexibility in the utilization of the FPGA http://www.deepdyve.com/assets/images/DeepDyve-Logo-lg.png ACM Transactions on Embedded Computing Systems (TECS) Association for Computing Machinery

Design and evaluation of random linear network coding Accelerators on FPGAs

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References (40)

Publisher
Association for Computing Machinery
Copyright
Copyright © 2013 by ACM Inc.
ISSN
1539-9087
DOI
10.1145/2512469
Publisher site
See Article on Publisher Site

Abstract

Design and Evaluation of Random Linear Network Coding Accelerators on FPGAs SUNWOO KIM, Hyundai Motor Company WON SEOB JEONG and WON W. RO, Yonsei University JEAN-LUC GAUDIOT, University of California, Irvine Network coding is a well-known technique used to enhance network throughput and reliability by applying special coding to data packets. One critical problem in practice, when using the random linear network coding technique, is the high computational overhead. More specifically, using this technique in embedded systems with low computational power might cause serious delays due to the complex Galois field operations and matrix handling. To this end, this article proposes a high-performance decoding logic for random linear network coding using field-programmable gate-array (FPGA) technology. We expect that the inherent reconfigurability of FPGAs will provide sufficient performance as well as programmability to cope with changes in the specification of the coding. The main design motivation was to improve the decoding delay by dividing and parallelizing the entire decoding process. Fast arithmetic operations are achieved by the proposed parallelized GF ALUs, which allow calculations with all the elements of a single row of a matrix to be performed concurrently. To improve the flexibility in the utilization of the FPGA

Journal

ACM Transactions on Embedded Computing Systems (TECS) – Association for Computing Machinery

Published: Aug 1, 2013

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