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Congestion-Aware Layout Design for High-Throughput Digital Microfluidic Biochips SUDIP ROY, Indian Institute of Technology, Kharagpur DEBASIS MITRA, National Institute of Technology, Durgapur BHARGAB B. BHATTACHARYA, Indian Statistical Institute, Kolkata KRISHNENDU CHAKRABARTY, Duke University Potential applications of digital microfluidic (DMF) biochips now include several areas of real-life applications like environmental monitoring, water and air pollutant detection, and food processing to name a few. In order to achieve sufficiently high throughput for these applications, several instances of the same bioassay may be required to be executed concurrently on different samples. As a straightforward implementation, several identical biochips can be integrated on a single substrate as a multichip to execute the assay for various samples concurrently. Controlling individual electrodes of such a chip by independent pins may not be acceptable since it increases the cost of fabrication. Thus, in order to keep the overall pin-count within an acceptable bound, all the respective electrodes of these individual pieces are connected internally underneath the chip so that they can be controlled with a single external control pin. In this article, we present an orientation strategy for layout of a multichip that reduces routing congestion and consequently facilitates wire routing for the electrode array.
ACM Journal on Emerging Technologies in Computing Systems (JETC) – Association for Computing Machinery
Published: Aug 1, 2012
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