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- Publisher
- Association for Computing Machinery
- Copyright
- Copyright © 2006 by ACM Inc.
- ISSN
- 1539-9087
- DOI
- 10.1145/1151074.1151081
- Publisher site
- See Article on Publisher Site
Abstract
Shared memory is a common interprocessor communication paradigm for single-chip multiprocessor platforms. Snoop-based cache coherence is a very successful technique that provides a clean shared-memory programming abstraction in general-purpose chip multiprocessors, but there is no consensus on its usage in resource-constrained multiprocessor systems on chips (MPSoCs) for embedded applications. This work aims at providing a comparative energy and performance analysis of cache-coherence support schemes in MPSoCs. Thanks to the use of a complete multiprocessor simulation platform, which relies on accurate technology-homogeneous power models, we were able to explore different cache-coherent shared-memory communication schemes for a number of cache configurations and workloads.
Journal
ACM Transactions on Embedded Computing Systems (TECS) – Association for Computing Machinery
Published: May 1, 2006