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Balancing Programmability and Silicon Efficiency of Heterogeneous Multicore Architectures

Balancing Programmability and Silicon Efficiency of Heterogeneous Multicore Architectures Balancing Programmability and Silicon Ef ciency of Heterogeneous Multicore Architectures ANDREI TERECHKO, JAN HOOGERBRUGGE, GHIATH ALKADI, SURENDRA GUNTUR, ANIRBAN LAHIRI, MARC DURANTON, CLEMENS WUST, PHILLIP CHRISTIE, AXEL NACKAERTS, and AATISH KUMAR, NXP Semiconductors, The Netherlands NXP Semiconductors, Belgium Multicore architectures provide scalable performance with a lower hardware design effort than single core processors. Our article presents a design methodology and an embedded multicore architecture, focusing on reducing the software design complexity and boosting the performance density. First, we analyze characteristics of the Task-Level Parallelism in modern multimedia workloads. These characteristics are used to formulate requirements for the programming model. Then we translate the programming model requirements to an architecture speci cation, including a novel low-complexity implementation of cache coherence and a hardware synchronization unit. Our evaluation demonstrates that the novel coherence mechanism substantially simpli es hardware design, while reducing the performance by less than 18% relative to a complex snooping technique. Compared to a single processor core, the multicores have already proven to be more area- and energy-ef cient. However, the multicore architectures in embedded systems still compete with highly ef cient function-speci c hardware accelerators. In this article we identify ve architectural methods to boost performance density http://www.deepdyve.com/assets/images/DeepDyve-Logo-lg.png ACM Transactions on Embedded Computing Systems (TECS) Association for Computing Machinery

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Publisher
Association for Computing Machinery
Copyright
Copyright © 2012 by ACM Inc.
ISSN
1539-9087
DOI
10.1145/2180887.2180890
Publisher site
See Article on Publisher Site

Abstract

Balancing Programmability and Silicon Ef ciency of Heterogeneous Multicore Architectures ANDREI TERECHKO, JAN HOOGERBRUGGE, GHIATH ALKADI, SURENDRA GUNTUR, ANIRBAN LAHIRI, MARC DURANTON, CLEMENS WUST, PHILLIP CHRISTIE, AXEL NACKAERTS, and AATISH KUMAR, NXP Semiconductors, The Netherlands NXP Semiconductors, Belgium Multicore architectures provide scalable performance with a lower hardware design effort than single core processors. Our article presents a design methodology and an embedded multicore architecture, focusing on reducing the software design complexity and boosting the performance density. First, we analyze characteristics of the Task-Level Parallelism in modern multimedia workloads. These characteristics are used to formulate requirements for the programming model. Then we translate the programming model requirements to an architecture speci cation, including a novel low-complexity implementation of cache coherence and a hardware synchronization unit. Our evaluation demonstrates that the novel coherence mechanism substantially simpli es hardware design, while reducing the performance by less than 18% relative to a complex snooping technique. Compared to a single processor core, the multicores have already proven to be more area- and energy-ef cient. However, the multicore architectures in embedded systems still compete with highly ef cient function-speci c hardware accelerators. In this article we identify ve architectural methods to boost performance density

Journal

ACM Transactions on Embedded Computing Systems (TECS)Association for Computing Machinery

Published: Jun 1, 2012

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