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Automatic RTL Test Generation from SystemC TLM Specifications

Automatic RTL Test Generation from SystemC TLM Specifications Automatic RTL Test Generation from SystemC TLM Speci cations MINGSONG CHEN, East China Normal University PRABHAT MISHRA, University of Florida DHRUBAJYOTI KALITA, Intel Corporation SystemC transaction-level modeling (TLM) is widely used to enable early exploration for both hardware and software designs. It can reduce the overall design and validation effort of complex system-on-chip (SOC) architectures. However, due to lack of automated techniques coupled with limited reuse of validation efforts between abstraction levels, SOC validation is becoming a major bottleneck. This article presents a novel top-down methodology for automatically generating register transfer-level (RTL) tests from SystemC TLM speci cations. It makes two important contributions: i) it proposes a method that can automatically generate TLM tests using various coverage metrics, and (ii) it develops a test re nement speci cation for automatically converting TLM tests to RTL tests in order to reduce overall validation effort. We have developed a tool which incorporates these activities to enable automated RTL test generation from SystemC TLM speci cations. Case studies using a router example and a 64-bit Alpha AXP pipelined processor demonstrate that our approach can achieve intended functional coverage of the RTL designs, as well as capture various functional errors and inconsistencies http://www.deepdyve.com/assets/images/DeepDyve-Logo-lg.png ACM Transactions on Embedded Computing Systems (TECS) Association for Computing Machinery

Automatic RTL Test Generation from SystemC TLM Specifications

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Publisher
Association for Computing Machinery
Copyright
Copyright © 2012 by ACM Inc.
ISSN
1539-9087
DOI
10.1145/2220336.2220350
Publisher site
See Article on Publisher Site

Abstract

Automatic RTL Test Generation from SystemC TLM Speci cations MINGSONG CHEN, East China Normal University PRABHAT MISHRA, University of Florida DHRUBAJYOTI KALITA, Intel Corporation SystemC transaction-level modeling (TLM) is widely used to enable early exploration for both hardware and software designs. It can reduce the overall design and validation effort of complex system-on-chip (SOC) architectures. However, due to lack of automated techniques coupled with limited reuse of validation efforts between abstraction levels, SOC validation is becoming a major bottleneck. This article presents a novel top-down methodology for automatically generating register transfer-level (RTL) tests from SystemC TLM speci cations. It makes two important contributions: i) it proposes a method that can automatically generate TLM tests using various coverage metrics, and (ii) it develops a test re nement speci cation for automatically converting TLM tests to RTL tests in order to reduce overall validation effort. We have developed a tool which incorporates these activities to enable automated RTL test generation from SystemC TLM speci cations. Case studies using a router example and a 64-bit Alpha AXP pipelined processor demonstrate that our approach can achieve intended functional coverage of the RTL designs, as well as capture various functional errors and inconsistencies

Journal

ACM Transactions on Embedded Computing Systems (TECS)Association for Computing Machinery

Published: Jul 1, 2012

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