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Hamming Distance (HD) is a popular similarity measure that is used widely in pattern matching applications, DNA sequencing, and binary error-correcting codes. In this article, we extend our previous work to prove that our HD circuit is scalable, tolerant to memristor model variability, and tolerant to device-to-device variation. We showed that the operation of our circuit under non-ideal fabrication conditions changes slightly, decreasing the correct classification rates for the MNIST handwritten digits dataset by <1%. Our circuit’s operation is independent of the memristor model used, as long as the model allows a reverse current. Because we leverage in-memory parallel computing, our circuit is n× faster than other HD circuits, where n is the number of HDs to be computed, and it consumes ≈100× − 1,000× less power compared to other memristive and CMOS HD circuits. Used in a full HD Associative Content Addressable Memory (ACAM), the proposed HD circuit consumes only 2.2% of the total system power. Our state-of-the-art, low-power, and fast HD circuit is relevant for a wide range of applications.
ACM Journal on Emerging Technologies in Computing Systems (JETC) – Association for Computing Machinery
Published: Mar 13, 2020
Keywords: Hamming distance
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