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An Improved Reversible Circuit Synthesis Approach using Clustering of ESOP Cubes

An Improved Reversible Circuit Synthesis Approach using Clustering of ESOP Cubes An Improved Reversible Circuit Synthesis Approach using Clustering of ESOP Cubes KAMALIKA DATTA, Indian Institute of Engineering Science and Technology, Shibpur GAURAV RATHI and INDRANIL SENGUPTA, Indian Institute of Technology Kharagpur HAFIZUR RAHAMAN, Indian Institute of Engineering Science and Technology, Shibpur The problem of reversible logic synthesis has drawn the attention of many researchers over the last two decades with growing emphasis on low-power design. Among the various synthesis approaches that have been reported, the ones based on compact circuit representations like Binary Decision Diagrams (BDD) and Exclusive-or Sum-Of-Products (ESOP) are interesting in the sense that they can handle large circuits with more than 100 inputs. The drawback of these approaches, however, is that the generated netlists are sub-optimal, and there is lot of scope for optimizing them. One of the best methods in this regard is an approach, where the ESOP cubes are grouped into sublists based on sharing among more than one outputs. In the work reported in this article, in contrast, an approach based on clustering the ESOP cubes based on their similarity with respect to input variables is presented, along with a technique to map each of the clusters into reversible gate netlists. This http://www.deepdyve.com/assets/images/DeepDyve-Logo-lg.png ACM Journal on Emerging Technologies in Computing Systems (JETC) Association for Computing Machinery

An Improved Reversible Circuit Synthesis Approach using Clustering of ESOP Cubes

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Publisher
Association for Computing Machinery
Copyright
Copyright © 2014 by ACM Inc.
ISSN
1550-4832
DOI
10.1145/2629543
Publisher site
See Article on Publisher Site

Abstract

An Improved Reversible Circuit Synthesis Approach using Clustering of ESOP Cubes KAMALIKA DATTA, Indian Institute of Engineering Science and Technology, Shibpur GAURAV RATHI and INDRANIL SENGUPTA, Indian Institute of Technology Kharagpur HAFIZUR RAHAMAN, Indian Institute of Engineering Science and Technology, Shibpur The problem of reversible logic synthesis has drawn the attention of many researchers over the last two decades with growing emphasis on low-power design. Among the various synthesis approaches that have been reported, the ones based on compact circuit representations like Binary Decision Diagrams (BDD) and Exclusive-or Sum-Of-Products (ESOP) are interesting in the sense that they can handle large circuits with more than 100 inputs. The drawback of these approaches, however, is that the generated netlists are sub-optimal, and there is lot of scope for optimizing them. One of the best methods in this regard is an approach, where the ESOP cubes are grouped into sublists based on sharing among more than one outputs. In the work reported in this article, in contrast, an approach based on clustering the ESOP cubes based on their similarity with respect to input variables is presented, along with a technique to map each of the clusters into reversible gate netlists. This

Journal

ACM Journal on Emerging Technologies in Computing Systems (JETC)Association for Computing Machinery

Published: Nov 5, 2014

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