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An Efficient Finite Field Multiplier Using Redundant Representation

An Efficient Finite Field Multiplier Using Redundant Representation An Ef cient Finite Field Multiplier Using Redundant Representation ASHKAN HOSSEINZADEH NAMIN, HUAPENG WU, and MAJID AHMADI, University of Windsor An ef cient word-level nite eld multiplier using redundant representation is proposed. The proposed multiplier has a signi cantly higher speed, compared to previously proposed word-level architectures using either redundant representation or optimal normal basis type I, at the expense of moderately higher area complexity. Furthermore, the new design out-performs other similar proposals when considering the product of area and delay as a measure of performance. ASIC Realization of the proposed design using TSMC ™s .18um CMOS technology for the binary eld size of 163 is also presented. Categories and Subject Descriptors: B.2.4 [Arithmetic and Logic Structures]: High-Speed Arithmetic General Terms: Algorithms, Security Additional Key Words and Phrases: Multiplier, nite eld, redundant representation, security ACM Reference Format: Namin, A. H., Wu, H., and Ahmadi, M. 2012. An ef cient nite eld multiplier using redundant representation. ACM Trans. Embed. Comput. Syst. 11, 2, Article 31 (July 2012), 14 pages. DOI = 10.1145/2220336.2220343 http://doi.acm.org/10.1145/2220336.2220343 1. INTRODUCTION Finite elds of characteristic two (binary elds) have been paid much attention recently, mainly because of their popular application in ef cient VLSI implementation http://www.deepdyve.com/assets/images/DeepDyve-Logo-lg.png ACM Transactions on Embedded Computing Systems (TECS) Association for Computing Machinery

An Efficient Finite Field Multiplier Using Redundant Representation

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Publisher
Association for Computing Machinery
Copyright
Copyright © 2012 by ACM Inc.
ISSN
1539-9087
DOI
10.1145/2220336.2220343
Publisher site
See Article on Publisher Site

Abstract

An Ef cient Finite Field Multiplier Using Redundant Representation ASHKAN HOSSEINZADEH NAMIN, HUAPENG WU, and MAJID AHMADI, University of Windsor An ef cient word-level nite eld multiplier using redundant representation is proposed. The proposed multiplier has a signi cantly higher speed, compared to previously proposed word-level architectures using either redundant representation or optimal normal basis type I, at the expense of moderately higher area complexity. Furthermore, the new design out-performs other similar proposals when considering the product of area and delay as a measure of performance. ASIC Realization of the proposed design using TSMC ™s .18um CMOS technology for the binary eld size of 163 is also presented. Categories and Subject Descriptors: B.2.4 [Arithmetic and Logic Structures]: High-Speed Arithmetic General Terms: Algorithms, Security Additional Key Words and Phrases: Multiplier, nite eld, redundant representation, security ACM Reference Format: Namin, A. H., Wu, H., and Ahmadi, M. 2012. An ef cient nite eld multiplier using redundant representation. ACM Trans. Embed. Comput. Syst. 11, 2, Article 31 (July 2012), 14 pages. DOI = 10.1145/2220336.2220343 http://doi.acm.org/10.1145/2220336.2220343 1. INTRODUCTION Finite elds of characteristic two (binary elds) have been paid much attention recently, mainly because of their popular application in ef cient VLSI implementation

Journal

ACM Transactions on Embedded Computing Systems (TECS)Association for Computing Machinery

Published: Jul 1, 2012

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