Get 20M+ Full-Text Papers For Less Than $1.50/day. Start a 14-Day Trial for You or Your Team.

Learn More →

A systematic approach for optimized bypass configurations for application-specific embedded processors

A systematic approach for optimized bypass configurations for application-specific embedded... A Systematic Approach for Optimized Bypass Configurations for Application-Specific Embedded Processors ¨ THORSTEN JUNGEBLUT and BORIS HUBENER, Bielefeld University MARIO PORRMANN, University of Paderborn ¨ ULRICH RUCKERT, Bielefeld University The diversity of today's mobile applications requires embedded processor cores with a high resource efficiency, that means, the devices should provide a high performance at low area requirements and power consumption. The fine-grained parallelism supported by multiple functional units of VLIW architectures offers a high throughput at reasonable low clock frequencies compared to single-core RISC processors. To efficiently utilize the processor pipeline, common system architectures have to cope with data hazards due to data dependencies between consecutive operations. On the one hand, such hazards can be resolved by complex forwarding circuits (i.e., a pipeline bypass) which forward intermediate results to a subsequent instruction. On the other hand, the pipeline bypass can strongly affect or even dominate the total resource requirements and degrade the maximum clock frequency. In this work the CoreVA VLIW architecture is used for the development and the analysis of application-specific bypass configurations. It is shown that many paths of a comprehensive bypass system are rarely used and may not be required for certain applications. For this http://www.deepdyve.com/assets/images/DeepDyve-Logo-lg.png ACM Transactions on Embedded Computing Systems (TECS) Association for Computing Machinery

A systematic approach for optimized bypass configurations for application-specific embedded processors

Loading next page...
 
/lp/association-for-computing-machinery/a-systematic-approach-for-optimized-bypass-configurations-for-HhxjXn01gv

References (33)

Publisher
Association for Computing Machinery
Copyright
Copyright © 2013 by ACM Inc.
ISSN
1539-9087
DOI
10.1145/2514641.2514645
Publisher site
See Article on Publisher Site

Abstract

A Systematic Approach for Optimized Bypass Configurations for Application-Specific Embedded Processors ¨ THORSTEN JUNGEBLUT and BORIS HUBENER, Bielefeld University MARIO PORRMANN, University of Paderborn ¨ ULRICH RUCKERT, Bielefeld University The diversity of today's mobile applications requires embedded processor cores with a high resource efficiency, that means, the devices should provide a high performance at low area requirements and power consumption. The fine-grained parallelism supported by multiple functional units of VLIW architectures offers a high throughput at reasonable low clock frequencies compared to single-core RISC processors. To efficiently utilize the processor pipeline, common system architectures have to cope with data hazards due to data dependencies between consecutive operations. On the one hand, such hazards can be resolved by complex forwarding circuits (i.e., a pipeline bypass) which forward intermediate results to a subsequent instruction. On the other hand, the pipeline bypass can strongly affect or even dominate the total resource requirements and degrade the maximum clock frequency. In this work the CoreVA VLIW architecture is used for the development and the analysis of application-specific bypass configurations. It is shown that many paths of a comprehensive bypass system are rarely used and may not be required for certain applications. For this

Journal

ACM Transactions on Embedded Computing Systems (TECS)Association for Computing Machinery

Published: Sep 1, 2013

There are no references for this article.