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A Synthesis Algorithm for Reconfigurable Single-Electron Transistor Arrays YUNG-CHIH CHEN, Chung Yuan Christian University SOUMYA EACHEMPATI, Intel Corporation CHUN-YAO WANG, National Tsing Hua University SUMAN DATTA, YUAN XIE, and VIJAYKRISHNAN NARAYANAN, Pennsylvania State University Reducing power consumption has become one of the primary challenges in chip design, and therefore significant efforts are being devoted to find holistic solutions on power reduction from the device level up to the system level. Among a plethora of low power devices that are being explored, single-electron transistors (SETs) at room temperature are particularly attractive. Although prior work has proposed a binary decision diagram-based reconfigurable logic architecture using SETs, it lacks an automatic synthesis algorithm for the architecture. Consequently, in this work, we develop a product-term-based approach that synthesizes a logic circuit by mapping all its product terms into the SET architecture. The experimental results show the effectiveness and efficiency of the proposed approach on a set of MCNC benchmarks. Categories and Subject Descriptors: B.6.3 [Logic Design]: Design Aids--Automatic synthesis General Terms: Algorithms Additional Key Words and Phrases: Automatic synthesis, binary decision diagram, single-electron transistor ACM Reference Format: Chen, Y.-C., Eachempati, S., Wang, C.-Y., Datta, S., Xie, Y., and Narayanan, V. 2013. A
ACM Journal on Emerging Technologies in Computing Systems (JETC) – Association for Computing Machinery
Published: Feb 1, 2013
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