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- Publisher
- Association for Computing Machinery
- Copyright
- Copyright © 2014 by ACM Inc.
- ISSN
- 1550-4832
- DOI
- 10.1145/2629542
- Publisher site
- See Article on Publisher Site
Abstract
A Synthesis Algorithm for 4-Bit Reversible Logic Circuits with Minimum Quantum Cost ZHIQIANG LI, Yangzhou University HANWU CHEN, Southeast University XIAOYU SONG and MAREK PERKOWSKI, Portland State University This article presents an algorithm which can quickly find the exact minimum solution to almost all of 4-bit reversible functions. We assume minimization of quantum cost (MQC). This algorithm is designed in the most memory-efficient way, or it will quickly run out of memory. Therefore, we construct the shortest coding of permutations, the topological compression and flexible data structures for the memory savings. First, hash tables are used for all 8-gate 4-bit circuits with the minimization of gate count (MGC) by using the GT library (with NOT, CNOT, Toffoli and Toffoli-4 gates). Second, we merge and split the hash tables, thus generating a single longer hash table for high-performance. Third, we synthesize these circuits with MQC by using the GTP library (with GT, Peres, and Inverted Peres gates) based on the hash table. Finally, according to the comparison of the QC of circuits, the algorithm can quickly converge for any 4-bit reversible circuit with MQC. By synthesizing all benchmark functions, in comparison with Szyprowski and Kerntopf [2011], the running time
Journal
ACM Journal on Emerging Technologies in Computing Systems (JETC) – Association for Computing Machinery
Published: Dec 30, 2014