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A Reconfigurable Architecture with Sequential Logic-Based Stochastic Computing

A Reconfigurable Architecture with Sequential Logic-Based Stochastic Computing A Reconfigurable Architecture with Sequential Logic-Based Stochastic Computing M. HASSAN NAJAFI, University of Minnesota PENG LI, Intel Corporation DAVID J. LILJA, University of Minnesota WEIKANG QIAN, University of Michigan-Shanghai Jiao Tong University Joint Institute KIA BAZARGAN and MARC RIEDEL, University of Minnesota Computations based on stochastic bit streams have several advantages compared to deterministic binary radix computations, including low power consumption, low hardware cost, high fault tolerance, and skew tolerance. To take advantage of this computing technique, previous work proposed a combinational logicbased reconfigurable architecture to perform complex arithmetic operations on stochastic streams of bits. The long execution time and the cost of converting between binary and stochastic representations, however, make the stochastic architectures less energy efficient than the deterministic binary implementations. This article introduces a methodology for synthesizing a given target function stochastically using finite-state machines (FSMs), and enhances and extends the reconfigurable architecture using sequential logic. Compared to the previous approach, the proposed reconfigurable architecture can save hardware area and energy consumption by up to 30% and 40%, respectively, while achieving a higher processing speed. Both stochastic reconfigurable architectures are much more tolerant of soft errors (bit flips) than the deterministic binary radix implementations, and their http://www.deepdyve.com/assets/images/DeepDyve-Logo-lg.png ACM Journal on Emerging Technologies in Computing Systems (JETC) Association for Computing Machinery

A Reconfigurable Architecture with Sequential Logic-Based Stochastic Computing

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Publisher
Association for Computing Machinery
Copyright
Copyright © 2017 by ACM Inc.
ISSN
1550-4832
DOI
10.1145/3060537
Publisher site
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Abstract

A Reconfigurable Architecture with Sequential Logic-Based Stochastic Computing M. HASSAN NAJAFI, University of Minnesota PENG LI, Intel Corporation DAVID J. LILJA, University of Minnesota WEIKANG QIAN, University of Michigan-Shanghai Jiao Tong University Joint Institute KIA BAZARGAN and MARC RIEDEL, University of Minnesota Computations based on stochastic bit streams have several advantages compared to deterministic binary radix computations, including low power consumption, low hardware cost, high fault tolerance, and skew tolerance. To take advantage of this computing technique, previous work proposed a combinational logicbased reconfigurable architecture to perform complex arithmetic operations on stochastic streams of bits. The long execution time and the cost of converting between binary and stochastic representations, however, make the stochastic architectures less energy efficient than the deterministic binary implementations. This article introduces a methodology for synthesizing a given target function stochastically using finite-state machines (FSMs), and enhances and extends the reconfigurable architecture using sequential logic. Compared to the previous approach, the proposed reconfigurable architecture can save hardware area and energy consumption by up to 30% and 40%, respectively, while achieving a higher processing speed. Both stochastic reconfigurable architectures are much more tolerant of soft errors (bit flips) than the deterministic binary radix implementations, and their

Journal

ACM Journal on Emerging Technologies in Computing Systems (JETC) – Association for Computing Machinery

Published: Jul 11, 2017

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