Access the full text.
Sign up today, get DeepDyve free for 14 days.
Loading next page...
/lp/association-for-computing-machinery/a-packet-switched-network-architecture-for-reconfigurable-computing-b9jVGP8XMo
References
References for this paper are not available at this time. We will be adding them shortly, thank you for your patience.
- Publisher
- Association for Computing Machinery
- Copyright
- The ACM Portal is published by the Association for Computing Machinery. Copyright © 2010 ACM, Inc.
- Subject
- Packet-switching networks
- ISSN
- 1539-9087
- DOI
- 10.1145/1596532.1596539
- Publisher site
- See Article on Publisher Site
Abstract
A packet-switched network architecture named Qnet and programming interface is presented that simplifies the integration of reconfigurable computing modules within a Field-Programmable Gate Array (FPGA). Qnet provides an abstraction layer to the designer of FPGA accelerator modules that hides the complexities of the system, while supporting a high degree of parallelism and performance. The architecture facilitates system design with pluggable, reusable modules. A network protocol is described that supports a three-party communication scheme between an initiator, a sender and a receiver. This protocol allows a master device to manage the state of other devices and the data flow within the system. An example using a high-level language is given. The Qnet architecture opens the computational power of FPGAs to computer scientists and software developers.
Journal
ACM Transactions on Embedded Computing Systems (TECS) – Association for Computing Machinery
Published: Oct 1, 2009