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A network congestion-aware memory subsystem for manycore

A network congestion-aware memory subsystem for manycore A Network Congestion-Aware Memory Subsystem for Manycore DONGKI KIM, SUNGJOO YOO, and SUNGGU LEE, POSTECH The network-on-chip (NoC) plays a crucial role in memory performance due to the fact that it can handle the majority of traffics from/to the DRAM memory controllers. However, there has been little work on the interplay between the NoC and memory controllers. In this article, we address a problem called network congestion-induced memory blocking and propose a novel memory controller, which performs memory access scheduling and network entry control in a network congestion-aware manner. In case of network congestion, in order to avoid performance degradation due to the blocking caused by data bound for congested regions in the NoC, the proposed memory controller favors requests and data associated with uncongested regions. In addition, in order to avoid the fairness problem of such a policy, we also propose a gradual method, which enables a trade-off between performance (in memory utilization) and fairness (in memory access latency). Experimental results show that the proposed method can offer up to 1.76 2.99 times improvement in memory utilization in the latency-tolerant designs. Categories and Subject Descriptors: C.2.m [Computer-Communication Networks]: Miscellaneous General Terms: Design, Performance Additional Key Words and http://www.deepdyve.com/assets/images/DeepDyve-Logo-lg.png ACM Transactions on Embedded Computing Systems (TECS) Association for Computing Machinery

A network congestion-aware memory subsystem for manycore

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References (40)

Publisher
Association for Computing Machinery
Copyright
Copyright © 2013 by ACM Inc.
ISSN
1539-9087
DOI
10.1145/2485984.2485998
Publisher site
See Article on Publisher Site

Abstract

A Network Congestion-Aware Memory Subsystem for Manycore DONGKI KIM, SUNGJOO YOO, and SUNGGU LEE, POSTECH The network-on-chip (NoC) plays a crucial role in memory performance due to the fact that it can handle the majority of traffics from/to the DRAM memory controllers. However, there has been little work on the interplay between the NoC and memory controllers. In this article, we address a problem called network congestion-induced memory blocking and propose a novel memory controller, which performs memory access scheduling and network entry control in a network congestion-aware manner. In case of network congestion, in order to avoid performance degradation due to the blocking caused by data bound for congested regions in the NoC, the proposed memory controller favors requests and data associated with uncongested regions. In addition, in order to avoid the fairness problem of such a policy, we also propose a gradual method, which enables a trade-off between performance (in memory utilization) and fairness (in memory access latency). Experimental results show that the proposed method can offer up to 1.76 2.99 times improvement in memory utilization in the latency-tolerant designs. Categories and Subject Descriptors: C.2.m [Computer-Communication Networks]: Miscellaneous General Terms: Design, Performance Additional Key Words and

Journal

ACM Transactions on Embedded Computing Systems (TECS)Association for Computing Machinery

Published: Jun 1, 2013

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