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Woo-Cheol Kwon, S. Yoo, Sungpack Hong, Byeong Min, Kyu-Myung Choi, Soo-Kwan Eo (2008)
A practical approach of memory access parallelization to exploit multiple off-chip DDR memories2008 45th ACM/IEEE Design Automation Conference
Jung Ahn, M. Erez, W. Dally (2006)
The Design Space of Data-Parallel Memory SystemsACM/IEEE SC 2006 Conference (SC'06)
Wooyoung Jang, D. Pan (2010)
Application-Aware NoC Design for Efficient SDRAM AccessIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 30
Zhao Zhang, Zhichun Zhu, Xiaodong Zhang (2000)
A permutation-based page interleaving scheme to reduce row-buffer conflicts and exploit data localityProceedings 33rd Annual IEEE/ACM International Symposium on Microarchitecture. MICRO-33 2000
(2010)
3D stacked memory design
Zhichun Zhu, Zhao Zhang (2005)
A performance comparison of DRAM memory system optimizations for SMT processors11th International Symposium on High-Performance Computer Architecture
Paul Gratz, Boris Grot, S. Keckler (2008)
Regional congestion awareness for load balance in networks-on-chip2008 IEEE 14th International Symposium on High Performance Computer Architecture
G. Sohi (1993)
High-Bandwidth Interleaved Memories for Vector Processors-A Simulation StudyIEEE Trans. Computers, 42
D. Abts, Natalie Jerger, John Kim, Dan Gibson, Mikko Lipasti (2009)
Achieving predictable performance through better memory controller placement in many-core CMPs
Arjun Singh, W. Dally, Brian Towles, A. Gupta (2004)
Globally Adaptive Load-Balanced Routing on ToriIEEE Computer Architecture Letters, 3
Jongman Kim, Dongkook Park, T. Theocharides, N. Vijaykrishnan, C. Das (2005)
A low latency router supporting adaptivity for on-chip interconnectsProceedings. 42nd Design Automation Conference, 2005.
G. Loh (2008)
3D-Stacked Memory Architectures for Multi-core Processors2008 International Symposium on Computer Architecture
O. Mutlu, T. Moscibroda (2008)
Parallelism-Aware Batch Scheduling: Enhancing both Performance and Fairness of Shared DRAM Systems2008 International Symposium on Computer Architecture
Erik Lindholm, J. Nickolls, S. Oberman, John Montrym (2008)
NVIDIA Tesla: A Unified Graphics and Computing ArchitectureIEEE Micro, 28
Single-chip cloud computer. http://techresearch.intel.com/articles/Tera-Scale/1826.htm
(2007)
Thousand Core Chips — A Technology Perspective
S. Rixner, W. Dally, U. Kapasi, P. Mattson, John Owens (2000)
Memory access schedulingProceedings of 27th International Symposium on Computer Architecture (IEEE Cat. No.RS00201)
M. Daneshtalab, M. Ebrahimi, P. Liljeberg, J. Plosila, H. Tenhunen (2010)
A Low-Latency and Memory-Efficient On-chip Network2010 Fourth ACM/IEEE International Symposium on Networks-on-Chip
S. Heithecker, R. Ernst (2005)
Traffic shaping for an FPGA based SDRAM controller with complex QoS requirementsProceedings. 42nd Design Automation Conference, 2005.
L. Peh, W. Dally (2001)
A delay model and speculative architecture for pipelined routersProceedings HPCA Seventh International Symposium on High-Performance Computer Architecture
Dong Woo, N. Seong, D. Lewis, H. Lee (2010)
An optimized 3D-stacked memory architecture by exploiting excessive, high-density TSV bandwidthHPCA - 16 2010 The Sixteenth International Symposium on High-Performance Computer Architecture
Jung-Sik Kim, C. Oh, Hocheol Lee, Donghyuk Lee, H. Hwang, S. Hwang, Byongwook Na, Joungwook Moon, Jin-Guk Kim, Hanna Park, Jang-Woo Ryu, Kiwon Park, Sanghee Kang, So-Young Kim, Hoyoung Kim, Jong-Min Bang, Hyunyoon Cho, M. Jang, C. Han, Jung-Bae Lee, K. Kyung, Joo-Sun Choi, Young-Hyun Jun (2011)
A 1.2V 12.8GB/s 2Gb mobile Wide-I/O DRAM with 4×128 I/Os using TSV-based stacking2011 IEEE International Solid-State Circuits Conference
O. Mutlu, T. Moscibroda (2007)
Stall-Time Fair Memory Access Scheduling for Chip Multiprocessors40th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO 2007)
Arjun Singh, W. Dally, A. Gupta, Brian Towles (2003)
GOAL: a load-balanced adaptive routing algorithm for torus networks30th Annual International Symposium on Computer Architecture, 2003. Proceedings.
Engin Ipek, O. Mutlu, José Martínez, R. Caruana (2008)
Self-Optimizing Memory Controllers: A Reinforcement Learning Approach2008 International Symposium on Computer Architecture
Dongki Kim, S. Yoo, Sunggu Lee (2010)
A Network Congestion-Aware Memory Controller2010 Fourth ACM/IEEE International Symposium on Networks-on-Chip
Amit Kumar, L. Peh, P. Kundu, N. Jha (2007)
Express virtual channels: towards the ideal interconnection fabric
(2010)
Xtensa customizable processors
(2011)
LPDDR3 and WideIO
Woo-Cheol Kwon, Sungpack Hong, S. Yoo, Byeong Min, Kyu-Myung Choi, Soo-Kwan Eo (2008)
An Open-Loop Flow Control Scheme Based on the Accurate Global Information of On-Chip Communication2008 Design, Automation and Test in Europe
B. Akesson, K. Goossens, M. Ringhofer (2007)
Predator: A predictable SDRAM memory controller2007 5th IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS)
I. Hur, Calvin Lin (2004)
Adaptive History-Based Memory Schedulers37th International Symposium on Microarchitecture (MICRO-37'04)
W. Dally, Hiromichi Aoki (1993)
Deadlock-Free Adaptive Routing in Multicomputer Networks Using Virtual ChannelsIEEE Trans. Parallel Distributed Syst., 4
AMBA3 (AXI) protocol. http://www.arm.com/products/solutions
Wooyoung Jang, D. Pan (2009)
An SDRAM-aware router for Networks-on-Chip2009 46th ACM/IEEE Design Automation Conference
Yoongu Kim, Dongsu Han, O. Mutlu, Mor Harchol-Balter (2010)
ATLAS: A scalable and high-performance scheduling algorithm for multiple memory controllersHPCA - 16 2010 The Sixteenth International Symposium on High-Performance Computer Architecture
Woo-Cheol Kwon, S. Yoo, Junhyung Um, Seh-Woong Jeong (2009)
In-network reorder buffer to improve overall NoC performance while resolving the in-order requirement problem2009 Design, Automation & Test in Europe Conference & Exhibition
Asit Mishra, Xiangyu Dong, Guangyu Sun, Yuan Xie, N. Vijaykrishnan, C. Das (2011)
Architecting on-chip interconnects for stacked 3D STT-RAM caches in CMPs2011 38th Annual International Symposium on Computer Architecture (ISCA)
Chang Lee, O. Mutlu, V. Narasiman, Y. Patt (2008)
Prefetch-Aware DRAM Controllers2008 41st IEEE/ACM International Symposium on Microarchitecture
B. Rau (1991)
Psfudo-randomly interleaved memory[1991] Proceedings. The 18th Annual International Symposium on Computer Architecture
A Network Congestion-Aware Memory Subsystem for Manycore DONGKI KIM, SUNGJOO YOO, and SUNGGU LEE, POSTECH The network-on-chip (NoC) plays a crucial role in memory performance due to the fact that it can handle the majority of traffics from/to the DRAM memory controllers. However, there has been little work on the interplay between the NoC and memory controllers. In this article, we address a problem called network congestion-induced memory blocking and propose a novel memory controller, which performs memory access scheduling and network entry control in a network congestion-aware manner. In case of network congestion, in order to avoid performance degradation due to the blocking caused by data bound for congested regions in the NoC, the proposed memory controller favors requests and data associated with uncongested regions. In addition, in order to avoid the fairness problem of such a policy, we also propose a gradual method, which enables a trade-off between performance (in memory utilization) and fairness (in memory access latency). Experimental results show that the proposed method can offer up to 1.76 2.99 times improvement in memory utilization in the latency-tolerant designs. Categories and Subject Descriptors: C.2.m [Computer-Communication Networks]: Miscellaneous General Terms: Design, Performance Additional Key Words and
ACM Transactions on Embedded Computing Systems (TECS) – Association for Computing Machinery
Published: Jun 1, 2013
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