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A Low-Power Variation-Aware Adaptive Write Scheme for Access-Transistor-Free Memristive Memory ~ AMIRALI GHOFRANI and MIGUEL-ANGEL LASTRAS-MONTANO, University of California, Santa Barbara SIDDHARTH GABA, University of Michigan, Ann Arbor MELIKA PAYVAND, University of California, Santa Barbara WEI LU, University of Michigan, Ann Arbor LUKE THEOGARAJAN and KWANG-TING CHENG, University of California, Santa Barbara Recent advances in access-transistor-free memristive crossbars have demonstrated the potential of memristor arrays as high-density and ultra-low-power memory. However, with considerable variations in the write-time characteristics of individual memristors, conventional fixed-pulse write schemes cannot guarantee reliable completion of the write operations and waste significant amount of energy. We propose an adaptive write scheme that adaptively adjusts the write pulses to address such variations in memristive arrays, resulting in 7×11× average energy saving in our case studies. Our scheme embeds an online monitor to detect the completion of a write operation and takes into account the parasitic effect of line-shared devices in access-transistor-free crossbars. This feature also helps shorten the test time of memory march algorithms by eliminating the need of a verifying read right after a write, which is commonly employed in the test sequences of march algorithms. Categories and Subject Descriptors: B.3 [Memory Structures] General
ACM Journal on Emerging Technologies in Computing Systems (JETC) – Association for Computing Machinery
Published: Aug 3, 2015
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