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A low-latency, high-throughput on-chip optical router architecture for future chip multiprocessors

A low-latency, high-throughput on-chip optical router architecture for future chip multiprocessors A Low-Latency, High-Throughput On-Chip Optical Router Architecture for Future Chip Multiprocessors MARK J. CIANCHETTI and DAVID H. ALBONESI, Cornell University Tens and eventually hundreds of processing cores are projected to be integrated onto future microprocessors, making the global interconnect a key component to achieving scalable chip performance within a given power envelope. While CMOS-compatible nanophotonics has emerged as a leading candidate for replacing global wires beyond the 16nm timeframe, on-chip optical interconnect architectures are typically limited in scalability or are dependent on comparatively slow electrical control networks. In this article, we present a hybrid electrical/optical router for future large scale, cache coherent multicore microprocessors. The heart of the router is a low-latency optical crossbar that uses predecoded source routing and switch state precon guration to transmit cache-line-sized packets several hops in a single clock cycle under contentionless conditions. Overall, our optical router achieves 2X better network performance than a state-of-the-art electrical baseline in a mesh topology while consuming 30% less network power. Categories and Subject Descriptors: C.2.1 [Computer-Communication Networks]: Network Architecture and Design ”Packet-switching networks General Terms: Design, Experimentation, Performance Additional Key Words and Phrases: Interconnect architecture, multiprocessor network, optical interconnect, optical switch ACM Reference Format: Cianchetti, M. http://www.deepdyve.com/assets/images/DeepDyve-Logo-lg.png ACM Journal on Emerging Technologies in Computing Systems (JETC) Association for Computing Machinery

A low-latency, high-throughput on-chip optical router architecture for future chip multiprocessors

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Publisher
Association for Computing Machinery
Copyright
Copyright © 2011 by ACM Inc.
ISSN
1550-4832
DOI
10.1145/1970406.1970411
Publisher site
See Article on Publisher Site

Abstract

A Low-Latency, High-Throughput On-Chip Optical Router Architecture for Future Chip Multiprocessors MARK J. CIANCHETTI and DAVID H. ALBONESI, Cornell University Tens and eventually hundreds of processing cores are projected to be integrated onto future microprocessors, making the global interconnect a key component to achieving scalable chip performance within a given power envelope. While CMOS-compatible nanophotonics has emerged as a leading candidate for replacing global wires beyond the 16nm timeframe, on-chip optical interconnect architectures are typically limited in scalability or are dependent on comparatively slow electrical control networks. In this article, we present a hybrid electrical/optical router for future large scale, cache coherent multicore microprocessors. The heart of the router is a low-latency optical crossbar that uses predecoded source routing and switch state precon guration to transmit cache-line-sized packets several hops in a single clock cycle under contentionless conditions. Overall, our optical router achieves 2X better network performance than a state-of-the-art electrical baseline in a mesh topology while consuming 30% less network power. Categories and Subject Descriptors: C.2.1 [Computer-Communication Networks]: Network Architecture and Design ”Packet-switching networks General Terms: Design, Experimentation, Performance Additional Key Words and Phrases: Interconnect architecture, multiprocessor network, optical interconnect, optical switch ACM Reference Format: Cianchetti, M.

Journal

ACM Journal on Emerging Technologies in Computing Systems (JETC) – Association for Computing Machinery

Published: Jun 1, 2011

References

  • All-optical switching on a silicon chip
    Almeida V. R.