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A Java Processor IP Design for Embedded SoC

A Java Processor IP Design for Embedded SoC A Java Processor IP Design for Embedded SoC CHUN-JEN TSAI, HAN-WEN KUO, ZIGANG LIN, ZI-JING GUO, and JUN-FU WANG, National Chiao Tung University In this article, we present a reusable Java processor IP for application processors of embedded systems. For the Java microarchitecture, we propose a low-cost stack memory design that supports a two-fold instruction folding pipeline and a low-complexity Java exception handling hardware. We also propose a mapping between the Java dynamic class loading model and the SoC platform-based design principle so that the Java core can be encapsulated as a reusable IP. To achieve this goal, a two-level method area with two on-chip circular buffers is proposed as an interface between the RISC core and the Java core. The proposed architecture is implemented on a Xilinx Virtex-5 FPGA device. Experimental results show that its performance has some advantages over other Java processors and a Java VM with JIT acceleration on a PowerPC platform. Categories and Subject Descriptors: C.3 [Computer Systems Organization]: Special-Purpose and Application-Based Systems--Real-time and embedded systems; D.3.4 [Programming Languages]: Processors--Run-time environments; B.7.1 [Integrated Circuits]: Types and Design Styles--Microprocessors and microcomputers General Terms: Design, Experimentation, Performance Additional Key Words and Phrases: Java accelerator, application processor http://www.deepdyve.com/assets/images/DeepDyve-Logo-lg.png ACM Transactions on Embedded Computing Systems (TECS) Association for Computing Machinery

A Java Processor IP Design for Embedded SoC

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Publisher
Association for Computing Machinery
Copyright
Copyright © 2015 by ACM Inc.
ISSN
1539-9087
DOI
10.1145/2629649
Publisher site
See Article on Publisher Site

Abstract

A Java Processor IP Design for Embedded SoC CHUN-JEN TSAI, HAN-WEN KUO, ZIGANG LIN, ZI-JING GUO, and JUN-FU WANG, National Chiao Tung University In this article, we present a reusable Java processor IP for application processors of embedded systems. For the Java microarchitecture, we propose a low-cost stack memory design that supports a two-fold instruction folding pipeline and a low-complexity Java exception handling hardware. We also propose a mapping between the Java dynamic class loading model and the SoC platform-based design principle so that the Java core can be encapsulated as a reusable IP. To achieve this goal, a two-level method area with two on-chip circular buffers is proposed as an interface between the RISC core and the Java core. The proposed architecture is implemented on a Xilinx Virtex-5 FPGA device. Experimental results show that its performance has some advantages over other Java processors and a Java VM with JIT acceleration on a PowerPC platform. Categories and Subject Descriptors: C.3 [Computer Systems Organization]: Special-Purpose and Application-Based Systems--Real-time and embedded systems; D.3.4 [Programming Languages]: Processors--Run-time environments; B.7.1 [Integrated Circuits]: Types and Design Styles--Microprocessors and microcomputers General Terms: Design, Experimentation, Performance Additional Key Words and Phrases: Java accelerator, application processor

Journal

ACM Transactions on Embedded Computing Systems (TECS) – Association for Computing Machinery

Published: Feb 17, 2015

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