Access the full text.
Sign up today, get DeepDyve free for 14 days.
A. Jalabert, S. Murali, L. Benini, G. Micheli (2004)
/spl times/pipesCompiler: a tool for instantiating application specific networks on chipProceedings Design, Automation and Test in Europe Conference and Exhibition, 2
Hangsheng Wang, Xinping Zhu, L. Peh, S. Malik (2002)
Orion: a power-performance simulator for interconnection networks35th Annual IEEE/ACM International Symposium on Microarchitecture, 2002. (MICRO-35). Proceedings.
J. Cong (1999)
An interconnect-centric design flow for nanometer technologies1999 International Symposium on VLSI Technology, Systems, and Applications. Proceedings of Technical Papers. (Cat. No.99TH8453)
Xinping Zhu, W. Qin, S. Malik (2004)
Modeling operation and microarchitecture concurrency for communication architectures with application to retargetable simulationInternational Conference on Hardware/Software Codesign and System Synthesis, 2004. CODES + ISSS 2004.
G. Micheli, L. Benini (2002)
Networks on chip: a new paradigm for systems on chip designProceedings 2002 Design, Automation and Test in Europe Conference and Exhibition
R. Siegmund, D. Müller (2003)
Efficient modeling and synthesis of on-chip communication protocols for network-on-chip designProceedings of the 2003 International Symposium on Circuits and Systems, 2003. ISCAS '03., 5
W. Wolf (2005)
Computers as components - principles of embedded computing system design
Yu Cao, Takashi Sato, M. Orshansky, D. Sylvester, C. Hu (2000)
New paradigm of predictive MOSFET and interconnect modeling for early circuit simulationProceedings of the IEEE 2000 Custom Integrated Circuits Conference (Cat. No.00CH37044)
J. Daveau, G. Marchioro, T. Ismail, A. Jerraya (1997)
Protocol selection and interface generation for HW-SW codesignIEEE Trans. Very Large Scale Integr. Syst., 5
A. Gouldstone, M. Kobinsky, S. Suresh (1999)
Integrated Circuits and Systems
M. Forsell (2002)
A Scalable High-Performance Computing Solution for Networks on ChipsIEEE Micro, 22
Mikael Millberg, E. Nilsson, R. Thid, Shashi Kumar, A. Jantsch (2004)
The Nostrum backbone-a communication protocol stack for Networks on Chip17th International Conference on VLSI Design. Proceedings.
M. Kuhlmann, S. Sapatnekar (2001)
Exact and efficient crosstalk estimationIEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 20
Jiang Xu, W. Wolf, J. Henkel, S. Chakradhar (2005)
A methodology for design, modeling, and analysis of networks-on-chip2005 IEEE International Symposium on Circuits and Systems
Adrijean Andriahantenaina, H. Charlery, A. Greiner, Laurent Mortiez, C. Zeferino (2003)
SPIN: a scalable, packet switched, on-chip micro-network2003 Design, Automation and Test in Europe Conference and Exhibition
W. Ho, T. Pinkston (2003)
A methodology for designing efficient on-chip interconnects on well-behaved communication patternsThe Ninth International Symposium on High-Performance Computer Architecture, 2003. HPCA-9 2003. Proceedings.
A. Pinto, L. Carloni, A. Sangiovanni-Vincentelli (2002)
Constraint-driven communication synthesisProceedings 2002 Design Automation Conference (IEEE Cat. No.02CH37324)
(2005)
Received February
Jiang Xu, W. Wolf (2003)
A wave-pipelined on-chip interconnect structure for networks-on-chips11th Symposium on High Performance Interconnects, 2003. Proceedings.
W. Dally, Brian Towles (2001)
Route packets, not wires: on-chip inteconnection networks
T. Wiegand, G. Sullivan, G. Bjøntegaard, A. Luthra (2003)
Overview of the H.264/AVC video coding standardIEEE Trans. Circuits Syst. Video Technol., 13
F. Karim, A. Nguyen, S. Dey (2002)
An Interconnect Architecture for Networking Systems on ChipsIEEE Micro, 22
W. Dally, Brian Towles (2001)
Route packets, not wires: on-chip interconnection networksProceedings of the 38th Design Automation Conference (IEEE Cat. No.01CH37232)
Shashi Kumar, A. Jantsch, Mikael Millberg, Johnny Öberg, J. Soininen, M. Forsell, Kari Tiensyrjä, A. Hemani (2002)
A network on chip architecture and design methodologyProceedings IEEE Computer Society Annual Symposium on VLSI. New Paradigms for VLSI Systems Design. ISVLSI 2002
Terry Ye, G. Micheli (2003)
Physical planning for on-chip multiprocessor networks and switch fabricsProceedings IEEE International Conference on Application-Specific Systems, Architectures, and Processors. ASAP 2003
K. Goossens, J. Dielissen, J. Meerbergen, P. Poplavko, A. Radulescu, E. Rijpkema, E. Waterlander, P. Wielage (2003)
Guaranteeing the Quality of Services in Networks on Chip
R. Hofmann, B. Drerup (2002)
Next generation CoreConnect/spl trade/ processor local bus architecture15th Annual IEEE International ASIC/SOC Conference
David Sigüenza-Tortosa, J. Nurmi (2002)
Proteo: A New Approach t o Network-on-Chip
Kyeong Ryu, Eung Shin, V. Mooney (2001)
A comparison of five different multiprocessor SoC bus architecturesProceedings Euromicro Symposium on Digital Systems Design
W. Wolf, I. Özer, T. Lv (2002)
Smart Cameras as Embedded SystemsComputer, 35
S. Murali, G. Micheli (2004)
SUNMAP: a tool for automatic topology selection and generation for NoCsProceedings. 41st Design Automation Conference, 2004.
Jian-Lin Liang, S. Swaminathan, R. Tessier (2000)
ASOC: a scalable, single-chip communications architectureProceedings 2000 International Conference on Parallel Architectures and Compilation Techniques (Cat. No.PR00622)
K. Lahiri, A. Raghunathan, S. Dey (2004)
Design space exploration for optimizing on-chip communication architecturesIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 23
W. Yuen, Evangeline Young (2003)
Slicing floorplan with clustering constraintIEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 22
M. Sgroi, M. Sheets, A. Mihal, K. Keutzer, S. Malik, J. Rabaey, A. Sangiovanni-Vincentelli (2001)
Addressing the system-on-a-chip interconnect woes through communication-based designProceedings of the 38th Design Automation Conference (IEEE Cat. No.01CH37232)
(2006)
A Design Methodology for Application-Specific Networks-on-Chip @BULLET 279
D. Wingard (2001)
MicroNetwork-based integration for SOCsProceedings of the 38th Design Automation Conference (IEEE Cat. No.01CH37232)
C. Zeferino, A. Susin (2003)
SoCIN: a parametric and scalable network-on-chip16th Symposium on Integrated Circuits and Systems Design, 2003. SBCCI 2003. Proceedings.
Jingcao Hu, R. Marculescu (2003)
Energy-aware mapping for tile-based NoC architectures under performance constraintsProceedings of the ASP-DAC Asia and South Pacific Design Automation Conference, 2003.
D. Flynn (1997)
AMBA: enabling reusable on-chip designsIEEE Micro, 17
(2010)
Technology trends.Biomedical instrumentation & technology, 44 6
A. Hemani, A. Jantsch, Shashi Kumar, A. Postula, Johnny Öberg, Mikael Millberg, Dan Lindqvist (2000)
Network on Chip : An architecture for billion transistor era
Joint Model Reference Software
With the help of HW/SW codesign, system-on-chip (SoC) can effectively reduce cost, improve reliability, and produce versatile products. The growing complexity of SoC designs makes on-chip communication subsystem design as important as computation subsystem design. While a number of codesign methodologies have been proposed for on-chip computation subsystems, many works are needed for on-chip communication subsystems. This paper proposes application-specific networks-on-chip (ASNoC) and its design methodology. ASNoC is used for two high-performance SoC applications. The methodology (1) can automatically generate optimized ASNoC for different applications, (2) can generate a corresponding distributed shared memory along with an ASNoC, (3) can use both recorded and statistical communication traces for cycle-accurate performance analysis, (4) is based on standardized network component library and floorplan to estimate power and area, (5) adapts an industrial-grade network modeling and simulation environment, OPNET, which makes the methodology ready to use, and (6) can be easily integrated into current HW/SW codesign flow. Using the methodology, ASNoC is generated for a H.264 HDTV decoder SoC and Smart Camera SoC. ASNoC and 2D mesh networks-on-chip are compared in performance, power, and area in detail. The comparison results show that ASNoC provide substantial improvements in power, performance, and cost compared to 2D mesh networks-on-chip. In the H.264 HDTV decoder SoC, ASNoC uses 39% less power, 59% less silicon area, 74% less metal area, 63% less switch capacity, and 69% less interconnection capacity to achieve 2X performance compared to 2D mesh networks-on-chip.
ACM Transactions on Embedded Computing Systems (TECS) – Association for Computing Machinery
Published: May 1, 2006
Read and print from thousands of top scholarly journals.
Already have an account? Log in
Bookmark this article. You can see your Bookmarks on your DeepDyve Library.
To save an article, log in first, or sign up for a DeepDyve account if you don’t already have one.
Copy and paste the desired citation format or use the link below to download a file formatted for EndNote
Access the full text.
Sign up today, get DeepDyve free for 14 days.
All DeepDyve websites use cookies to improve your online experience. They were placed on your computer when you launched this website. You can change your cookie settings through your browser.